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Seoul National University

Seoul National University. Sequential Implementation. Seoul National University. Byte. 0. 1. 2. 3. 4. 5. nop. 1. 0. halt. 0. 0. cmovXX rA , rB. 2. fn. rA. rB. irmovl V , rB. 3. 0. 8. rB. V. rmmovl rA , D ( rB ). 4. 0. rA. rB. D. mrmovl D ( rB ), rA. 5. 0.

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Seoul National University

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  1. Seoul National University Sequential Implementation

  2. Seoul National University Byte 0 1 2 3 4 5 nop 1 0 halt 0 0 cmovXXrA, rB 2 fn rA rB irmovl V, rB 3 0 8 rB V rmmovl rA, D(rB) 4 0 rA rB D mrmovl D(rB), rA 5 0 rA rB D OPlrA, rB 6 fn rA rB jXXDest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushlrA A 0 rA 8 poplrA B 0 rA 8 Y86 Instruction Set #1

  3. Seoul National University Byte 0 1 2 3 4 5 nop 1 0 halt 0 0 cmovXXrA, rB 2 fn rA rB irmovl V, rB 3 0 8 rB V rmmovl rA, D(rB) 4 0 rA rB D 2 0 mrmovl D(rB), rA 5 0 rA rB D 2 1 OPlrA, rB 6 fn rA rB 2 2 jXXDest 7 fn Dest 2 3 call Dest 8 0 Dest 2 4 ret 9 0 2 5 pushlrA A 0 rA 8 2 6 poplrA B 0 rA 8 Y86 Instruction Set #2 rrmovl cmovle cmovl cmove cmovne cmovge cmovg

  4. Seoul National University Byte 0 1 2 3 4 5 nop 1 0 addl 6 0 halt 0 0 subl 6 1 cmovXXrA, rB 2 fn rA rB andl 6 2 irmovl V, rB 3 0 8 rB V xorl 6 3 rmmovl rA, D(rB) 4 0 rA rB D mrmovl D(rB), rA 5 0 rA rB D OPlrA, rB 6 fn rA rB jXXDest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushlrA A 0 rA 8 poplrA B 0 rA 8 Y86 Instruction Set #3

  5. Seoul National University Byte 0 1 2 3 4 5 nop 1 0 halt 0 0 cmovXXrA, rB 2 fn rA rB irmovl V, rB 3 0 8 rB V rmmovl rA, D(rB) 4 0 rA rB D jmp 7 0 mrmovl D(rB), rA 5 0 rA rB D jle 7 1 OPlrA, rB 6 fn rA rB jl 7 2 jXXDest 7 fn Dest je 7 3 call Dest 8 0 Dest jne 7 4 ret 9 0 jge 7 5 pushlrA A 0 rA 8 jg 7 6 poplrA B 0 rA 8 Y86 Instruction Set #4

  6. Seoul National University valA Register file srcA A valW W dstW valB srcB B Clock fun A MUX 0 A L U = B 1 Clock Building Blocks • Combinational Logic • Compute Boolean functions of inputs • Continuously respond to input changes • Operate on data and implement control • Storage Elements • Store bits • Addressable memories • Non-addressable registers • Loaded only as clock rises

  7. Seoul National University Hardware Control Language • Very simple hardware description language • Can only express limited aspects of hardware operation • Parts we want to explore and modify • Data Types • bool: Boolean • a, b, c, … • int: words • A, B, C, … • Does not specify word size---bytes, 32-bit words, … • Statements • bool a = bool-expr; • int A = int-expr;

  8. Seoul National University HCL Operations • Classify by type of value returned • Boolean Expressions • Logic Operations • a && b, a || b, !a • Word Comparisons • A == B, A != B, A < B, A <= B, A >= B, A > B • Set Membership • A in { B, C, D } • Same as A == B || A == C || A == D • Word Expressions • Case expressions • [ a : A; b : B; c : C ] • Evaluate test expressions a, b, c, … in sequence • Return word expression A, B, C, … for first successful test

  9. Seoul National University SEQ Hardware Structure newPC PC • “State” • Register File • Memory • Instruction: for reading instructions • Data: for reading/writing program data • Program counter register (PC) • Condition code register (CC) • Instruction Flow • Read instruction at address specified by PC • Process through stages • Update the “state” including the program counter valE , valM Write back valM Data Data Memory memory memory Addr , Data valE CC CC ALU ALU Execute Cnd aluA , aluB valA , valB srcA , srcB Decode A A B B dstA , dstB M M Register Register Register Register file file file file E E icode ifun valP rA , rB valC Instruction PC Instruction PC Fetch memory increment memory inc PC

  10. Seoul National University SEQ Stages newPC PC • Fetch • Read instruction from instruction memory • Decode • Read from registers • Execute • Compute value or address • Memory • Read from or write to memory • Write Back • Write to registers • PC • Update program counter valE , valM Write back valM Data Data Memory memory memory Addr , Data valE CC CC ALU ALU Execute Cnd aluA , aluB valA , valB srcA , srcB Decode A A B B dstA , dstB M M Register Register Register Register file file file file E E icode ifun valP rA , rB valC Instruction PC Instruction PC Fetch memory increment memory inc PC

  11. Seoul National University 5 0 rA rB Instruction Decoding Optional Optional D icode ifun rA rB valC • Instruction Format • Instruction byte icode:ifun • Optional register byte rA:rB • Optional constant word valC

  12. Seoul National University OPlrA, rB 6 fn rA rB Executing Arith./Logical Operation • Memory • Do nothing • Write back • Update register • PC Update • Increment PC by 2 • Fetch • Read 2 bytes • Decode • Read operand registers • Execute • Perform operation • Set condition codes

  13. Seoul National University Fetch icode:ifun  M1[PC] rA:rB  M1[PC+1] valP  PC+2 Decode valA  R[rA] valB  R[rB] Execute valE valB OP valA Set CC Memory Write back R[rB]  valE PC update PC  valP Stage Computation: Arith/Log. Ops OPlrA, rB • Formulate instruction execution as sequence of simple steps • Use the same general form for all instructions

  14. Seoul National University rA rB 4 0 rmmovlrA, D(rB) D Executing rmmovl • Fetch • Read 6 bytes • Decode • Read operand registers • Execute • Compute effective address • Memory • Write to memory • Write back • Do nothing • PC Update • Increment PC by 6

  15. Seoul National University Fetch icode:ifun  M1[PC] rA:rB  M1[PC+1] valC  M4[PC+2] valP  PC+6 Decode valA  R[rA] valB  R[rB] Execute valE  valB + valC Memory M4[valE]  valA Write back PC update PC  valP Stage Computation: rmmovl rmmovl rA, D(rB)

  16. Seoul National University Fetch icode:ifun  M1[PC] rA:rB  M1[PC+1] valC  M4[PC+2] valP  PC+6 Decode valB R[rB] Execute valE  valB + valC Memory valMM4[valE] Write back PC update PC  valP Stage Computation: mrmovl mrmovlD(rB), rA R[rA]  valM

  17. Seoul National University Fetch icode:ifun  M1[PC] rA:rB  M1[PC+1] valP PC+2 Decode valA  R[rA] Execute valE 0 + valA Memory Write back PC update PC  valP Stage Computation: rrmovl rrmovlrA, rB R[rB]  valE

  18. Seoul National University Fetch icode:ifun  M1[PC] rA:rB  M1[PC+1] valC  M4[PC+2] valP  PC+6 Decode Execute valE 0+ valC Memory Write back PC update PC  valP Stage Computation: irmovl irmovlV, rB R[rB]  valE

  19. Seoul National University Fetch icode:ifun  M1[PC] rA:rB  M1[PC+1] valP  PC+2 Decode valA R[rA] valB R[%esp] Execute valE valB + (-4) Memory M4[valA] valA Write back R[%esp]  valE PC update PC  valP Stage Computation: pushl pushlrA

  20. Seoul National University Fetch icode:ifun  M1[PC] rA:rB  M1[PC+1] valP  PC+2 Decode valA R[%esp] valB R[%esp] Execute valE  valB + 4 Memory valM  M4[valA] Write back R[%esp]  valE R[rA]  valM PC update PC  valP Stage Computation: popl popl rA

  21. Seoul National University Fetch icode:ifun  M1[PC] valC  M4[PC+1] valP  PC+5 Decode Execute CndCond(CC,ifun) Memory Write back PC update PC  Cnd? valC : valP Stage Computation: Jumps jXX Dest

  22. Seoul National University Decode valB  R[%esp] Execute valE valB + (-4) Memory M4[valE]  valP Write back R[%esp]  valE PC update PC  valC Stage Computation: call call Dest Fetch icode:ifun  M1[PC] valC M4[PC+1] valP PC+5

  23. Seoul National University Fetch icode:ifun  M1[PC] Decode valA R[%esp] valB  R[%esp] Execute valE  valB + 4 Memory valM  M4[valA] Write back R[%esp]  valE PC update PC  valM Stage Computation: ret ret valP PC+1

  24. Seoul National University Stage Computation (More Structured) OPl rA, rB Fetch icode,ifun icode:ifun  M1[PC] Read instruction byte rA,rB rA:rB  M1[PC+1] Read register byte valC [Read constant word] valP valP  PC+2 Compute next PC Decode valA, srcA valA  R[rA] Read operand A valB, srcB valB  R[rB] Read operand B Execute valE valE  valB OP valA Perform ALU operation Cond code Set CC Set condition code register Memory valM [Memory read/write] Write back dstE R[rB]  valE Write back ALU result dstM [Write back memory result] PC update PC PC  valP Update PC • All instructions follow the same general pattern • Differ in what gets computed during each step

  25. Seoul National University Stage Computation (More Structured) call Dest Fetch icode,ifun icode:ifun  M1[PC] Read instruction byte rA,rB [Read register byte] valC valC  M4[PC+1] Read constant word valP valP  PC+5 Compute next PC Decode valA, srcA [Read operand A] valB, srcB valB  R[%esp] Read operand B Execute valE valE valB + (-4) Perform ALU operation Cond code [Set condition code reg.] Memory valM M4[valE]  valP [Memory read/write] Write back dstE R[%esp]  valE [Write back ALU result] dstM Write back memory result PC update PC PC  valC Update PC • All instructions follow the same general pattern • Differ in what gets computed during each step

  26. Seoul National University Computed Values • Fetch icode Instruction code ifun Instruction function rA Instr. Register A rB Instr. Register B valC Instruction constant valP Incremented PC • Decode srcA Register ID A srcB Register ID B dstE Destination Register E dstM Destination Register M valA Register value A valB Register value B • Execute • valE ALU result • Cnd Branch/move flag • Memory • valM Value from memory

  27. Seoul National University SEQ Hardware • Key • Blue boxes : predesigned hardware blocks • E.g., memories, ALU • Gray boxes : control logic • Described in HCL • White ovals : labels for signals • Thick lines : 32-bit word values • Thin lines : 4-8 bit values • Dotted lines : 1-bit values

  28. Seoul National University Fetch Logic #1 • Predefined Blocks • PC : Register containing PC • Instruction memory : Read 6 bytes (PC to PC+5) • Signal invalid address • Split : Divide instruction byte into icode and ifun • Align : Get fields for rA, rB, and valC icode ifun rA rB valC valP Need valC PC increment Instr valid Need regids icode ifun Split Align Byte 0 Bytes 1-5 Instruction memory imem_error PC

  29. Seoul National University Fetch Logic #2 • Control Logic • Instr. Valid • Is this instruction valid? • icode, ifun • Generate no-op if invalid address • Need regids • Does this instruction have a register byte? • Need valC • Does this instruction have a constant word? icode ifun rA rB valC valP Need valC PC increment Instr valid Need regids icode ifun Split Align Byte 0 Bytes 1-5 Instruction memory imem_error PC

  30. Seoul National University Fetch Control Logic in HCL # Determine instruction code inticode = [ imem_error: INOP; 1: imem_icode; ]; # Determine instruction function intifun = [ imem_error: FNONE; 1: imem_ifun; ]; icode ifun Split Byte 0 Instruction memory imem_error PC

  31. Seoul National University nop 1 0 halt 0 0 cmovXXrA, rB 2 fn rA rB irmovl V, rB 3 0 8 rB V rmmovl rA, D(rB) 4 0 rA rB D mrmovlD(rB), rA 5 0 rA rB D OPlrA, rB 6 fn rA rB jXXDest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushlrA A 0 rA 8 poplrA B 0 rA 8 Fetch Control Logic in HCL boolneed_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL }; boolinstr_valid = icode in {IHALT, INOP, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL };

  32. Seoul National University Decode Logic • Register File • Read ports A, B • Write ports E, M • Addresses are register IDs or 15 (0xF) (no access) Cnd valA valB valM valE A B Register file M E dstE dstM srcA srcB • Control Logic • srcA, srcB: read port addresses • dstE, dstM: write port addresses dstE dstM srcA srcB icode rA rB • Signals • Cnd: Indicate whether or not to perform conditional move -> Computed in Execute stage

  33. OPl rA, rB Seoul National University Decode valA  R[rA] Read operand A A Source cmovXXrA, rB Decode valA  R[rA] Read operand A rmmovlrA, D(rB) Decode valA  R[rA] Read operand A popl rA Decode valA  R[%esp] Read stack pointer jXX Dest Decode No operand call Dest Decode No operand ret Decode valA  R[%esp] Read stack pointer intsrcA = [ icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : rA; icode in { IPOPL, IRET } : RESP; 1 : RNONE; # Don't need register ];

  34. OPl rA, rB Seoul National University Write-back R[rB]  valE Write back result E Destination cmovXXrA, rB Conditionally write back result Write-back R[rB]  valE rmmovl rA, D(rB) Write-back None popl rA Write-back R[%esp]  valE Update stack pointer jXX Dest Write-back None call Dest Write-back R[%esp]  valE Update stack pointer ret Write-back R[%esp]  valE Update stack pointer intdstE = [ icode in { IRRMOVL } && Cnd : rB; icode in { IIRMOVL, IOPL} : rB; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't write any register ];

  35. Seoul National University Execute Logic • Units • ALU • Implements 4 required functions • Generates condition code values • CC • Register with 3 condition code bits • cond • Computes conditional jump/move flag • Control Logic • Set CC: Should condition code register be loaded? • ALU A: Input A to ALU • ALU B: Input B to ALU • ALU fun: What function should ALU compute? Cnd valE cond ALU fun. ALU CC Set CC ALU A ALU B icode ifun valC valA valB

  36. OPl rA, rB Seoul National University Execute valE  valB OP valA Perform ALU operation ALU A Input cmovXXrA, rB Execute valE 0 + valA Pass valA through ALU rmmovl rA, D(rB) Execute valE  valB + valC Compute effective address popl rA Execute valE  valB + 4 Increment stack pointer jXX Dest Execute No operation call Dest Execute valE  valB + –4 Decrement stack pointer ret Execute valE  valB + 4 Increment stack pointer intaluA = [ icode in { IRRMOVL, IOPL } : valA; icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valC; icode in { ICALL, IPUSHL } : -4; icode in { IRET, IPOPL } : 4; # Other instructions don't need ALU ];

  37. Seoul National University ALU Operation OPl rA, rB Execute valE valBOPvalA Perform ALU operation cmovXXrA, rB Execute valE 0 +valA Pass valA through ALU rmmovl rA, D(rB) Execute valE valB+valC Compute effective address popl rA Execute valE valB+ 4 Increment stack pointer jXX Dest Execute No operation call Dest Execute valE valB+ –4 Decrement stack pointer ret Execute valE valB+ 4 Increment stack pointer intalufun = [ icode == IOPL : ifun; 1 : ALUADD; ];

  38. Seoul National University Memory Logic • Memory • Reads or writes memory word • Control Logic • stat: What is instruction status? • Mem. read: should word be read? • Mem. write: should word be written? • Mem. addr.: Select address • Mem. data.: Select data Stat valM stat dmem_error data out Mem. read read instr_valid Data memory imem_error Mem. write write data in Mem. addr Mem. data icode valE valA valP

  39. Seoul National University Instruction Status • Control Logic • stat: What is instruction status? ## Determine instruction status int Stat = [ imem_error || dmem_error : SADR; !instr_valid: SINS; icode == IHALT : SHLT; 1 : SAOK; ]; Stat valM stat dmem_error data out Mem. read read instr_valid Data memory imem_error Mem. write write data in Mem. addr Mem. data icode valE valA valP

  40. Seoul National University OPl rA, rB Memory No operation rmmovl rA, D(rB) popl rA jXX Dest Memory Memory Memory Memory M4[valE]  valP valM  M4[valA] M4[valE]  valA valM  M4[valA] Write return value on stack Write value to memory Read return address Read from stack Memory No operation call Dest ret Memory Address intmem_addr = [ icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : valE; icode in { IPOPL, IRET } : valA; # Other instructions don't need address ];

  41. Seoul National University OPl rA, rB Memory No operation rmmovl rA, D(rB) popl rA jXX Dest Memory Memory Memory Memory M4[valE] valA valMM4[valA] valMM4[valA] M4[valE]  valP Read from stack Read return address Write value to memory Write return value on stack Memory No operation call Dest ret Memory Read boolmem_read = icode in { IMRMOVL, IPOPL, IRET };

  42. Seoul National University PC Update Logic • New PC • Select next value of PC PC New PC icode Cnd valC valM valP

  43. Seoul National University OPl rA, rB rmmovl rA, D(rB) popl rA jXX Dest call Dest PC update PC update PC update PC update PC update PC update PC  valC PC  valP PC  Cnd? valC : valP PC  valM PC  valP PC  valP Set PC to return address Update PC Update PC Set PC to destination Update PC Update PC ret PC Update intnew_pc = [ icode == ICALL : valC; icode == IJXX && Cnd: valC; icode == IRET : valM; 1 : valP; ];

  44. Seoul National University SEQ Operation • State • PC register • Cond. Code register • Data memory • Register file All updated as clock rises • Combinational Logic • ALU • Control logic • Memory reads • Instruction memory • Register file • Data memory

  45. Seoul National University SEQ Operation #2 • combinational logic starting to react to state changes

  46. Seoul National University SEQ Operation #3 • combinational logic generates results for addl instruction

  47. Seoul National University SEQ Operation #4 • state set according to addlinstruction • combinational logic starting to react to state changes

  48. Seoul National University SEQ Operation #5 • combinational logic generates results for je instruction

  49. Seoul National University SEQ Summary • Implementation • Express every instruction as a series of simple steps • Follow the same general flow for each instruction type • Assemble registers, memories, predesigned combinational blocks • Connect with control logic • Limitations • Too slow to be practical • In one cycle, must propagate through instruction memory, register file, ALU, and data memory • Would need to run clock very slowly • Hardware units only active for fraction of clock cycle

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