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Chapter 2

Chapter 2. Instructions: Language of the Computer. Instruction Set. §2.1 Introduction. The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects in common Early computers had very simple instruction sets Simplified implementation

vivian-kirkland
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Chapter 2

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  1. Chapter 2 Instructions: Language of the Computer

  2. Instruction Set §2.1 Introduction • The repertoire of instructions of a computer • Different computers have different instruction sets • But with many aspects in common • Early computers had very simple instruction sets • Simplified implementation • Many modern computers also have simple instruction sets Chapter 2 — Instructions: Language of the Computer — 2

  3. The MIPS Instruction Set • Used as the example throughout the book • Stanford MIPS commercialized by MIPS Technologies (www.mips.com) • Large share of embedded core market • Applications in consumer electronics, network/storage equipment, cameras, printers, … • Typical of many modern ISAs • See MIPS Reference Data tear-out card, and Appendixes B and E Chapter 2 — Instructions: Language of the Computer — 3

  4. The ARM Instruction Set • Used as the example in chapters 2 and 3 • Most popular 32-bit instruction set in the world (www.arm.com) • 4 Billion shipped in 2008 • Large share of embedded core market • Applications include mobile phones, consumer electronics, network/storage equipment, cameras, printers, … • Typical of many modern RISC ISAs • See ARM Assembler instructions, their encoding and instruction cycle timings in appendixes B1,B2 and B3 (CD-ROM) Chapter 2 — Instructions: Language of the Computer — 4

  5. SW in high level language SW in assembly language (instruction set) HW implementation Why study instruction sets? • Interface of hardware and software • Efficient mapping: • Software in high level language  software in assembly language (instruction set) (Chapter 2) • Impact SW cost/performance • Instruction set  hardware implementation (Chapter 3&4) • Impact HW cost/performance

  6. C, C++, SystemC, etc. Assembly programming Verilog/VHDL Electronic System Design Laboratory • GOAL: • Training of students who are able to master the hardware/software co-design, co-simulation, co-verification.

  7. What is “Computer Architecture”? Application • Coordination of many levels of abstraction • Under a rapidly changing set of forces • Design, Measurement, andEvaluation Operating System Compiler Firmware Instruction Set Architecture Instr. Set Proc. I/O system Datapath & Control Digital Design Circuit Design Layout

  8. Instructions: • Language of the Machine • We’ll be working with the MIPS instruction set architecture • similar to other architectures developed since the 1980's • Almost 100 million MIPS processors manufactured in 2002 • used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, …

  9. Arithmetic Operations • Add and subtract, three operands • Two sources and one destination add a, b, c # a gets b + c • All arithmetic operations have this form • Design Principle 1: Simplicity favours regularity • Regularity makes implementation simpler • Simplicity enables higher performance at lower cost §2.2 Operations of the Computer Hardware Chapter 2 — Instructions: Language of the Computer — 9

  10. Arithmetic Example (MIPS) • C code: f = (g + h) - (i + j); • Compiled MIPS code: add t0, g, h # temp t0 = g + hadd t1, i, j # temp t1 = i + jsub f, t0, t1 # f = t0 - t1 Chapter 2 — Instructions: Language of the Computer — 10

  11. Arithmetic Example (ARM) • C code: f = (g + h) - (i + j); • Compiled ARM code: ADD t0, g, h ; temp t0 = g + hADD t1, i, j ; temp t1 = i + jSUB f, t0, t1 ; f = t0 - t1 Chapter 2 — Instructions: Language of the Computer — 11

  12. Register Operands (MIPS) • Arithmetic instructions use registeroperands • MIPS has a 32 × 32-bit register file • Use for frequently accessed data • Numbered 0 to 31 • 32-bit data called a “word” • Assembler names • $t0, $t1, …, $t9 for temporary values • $s0, $s1, …, $s7 for saved variables • Design Principle 2: Smaller is faster • c.f. main memory: millions of locations §2.3 Operands of the Computer Hardware Chapter 2 — Instructions: Language of the Computer — 12

  13. Register Operands (ARM) • Arithmetic instructions use registeroperands • ARM has a 16 × 32-bit register file • Use for frequently accessed data • Registers numbered 0 to 15 (r0 to r15) • 32-bit data called a “word” • Design Principle 2: Smaller is faster • c.f. main memory: millions of locations §2.3 Operands of the Computer Hardware Chapter 2 — Instructions: Language of the Computer — 13

  14. Control Input Memory Datapath Output Processor I/O Registers vs. Memory • Arithmetic instructions operands must be registers, — only 32 (MIPS) or 16 (ARM) registers provided • Compiler associates variables with registers • What about programs with lots of variables? Registers

  15. Register Operand Example (MIPS) • C code: f = (g + h) - (i + j); • f, …, j in $s0, …, $s4 • Compiled MIPS code: add $t0, $s1, $s2add $t1, $s3, $s4sub $s0, $t0, $t1 Chapter 2 — Instructions: Language of the Computer — 15

  16. Register Operand Example (ARM) • C code: f = (g + h) - (i + j); • f, …, j in registers r0, …,r4 • r5 and r6 are temporary registers • Compiled ARM code: ADD r5,r0,r1 ;register r5 contains g + h ADD r6,r2,r3 ;register r6 contains i + j SUB r4,r5,r6 ;r4 gets r5-r6 Chapter 2 — Instructions: Language of the Computer — 16

  17. Memory Organization • Viewed as a large, single-dimension array, with an address. • A memory address is an index into the array • "Byte addressing" means that the index points to a byte of memory. 0 8 bits of data 1 8 bits of data 2 8 bits of data 3 8 bits of data 4 8 bits of data 5 8 bits of data 6 8 bits of data ...

  18. Memory Organization • Bytes are nice, but most data items use larger "words" • For MIPS, a word is 32 bits or 4 bytes. • 232 bytes with byte addresses from 0 to 232-1 • 230 words with byte addresses 0, 4, 8, ... 232-4 • Words are aligned i.e., what are the least 2 significant bits of a word address? 0 32 bits of data 4 32 bits of data Registers hold 32 bits of data 8 32 bits of data 12 32 bits of data ...

  19. Memory Operands • Main memory used for composite data • Arrays, structures, dynamic data • To apply arithmetic operations • Load values from memory into registers • Store result from register to memory • Memory is byte addressed • Each address identifies an 8-bit byte • Words are aligned in memory • Address must be a multiple of 4 • MIPS is Big Endian • Most-significant byte at least address of a word • c.f. Little Endian: least-significant byte at least address Chapter 2 — Instructions: Language of the Computer — 19

  20. Placing a 32-bit word into memory in bytes • Big Endian • Little Endian 0 0 Least significant Most significant 1 1 : : 2 2 : : 3 3 Least significant Most significant 4 4 5 5 6 6 ... ... Chapter 2 — Instructions: Language of the Computer — 20

  21. Memory Operand Example 1 (MIPS) • C code: g = h + A[8]; • g in $s1, h in $s2, base address of A in $s3 • Compiled MIPS code: • Index 8 requires offset of 32 • 4 bytes per word lw $t0, 32($s3) # $t0 <-m[$s3+32]add $s1, $s2, $t0 offset base register Chapter 2 — Instructions: Language of the Computer — 21

  22. Memory Operand Example 1 (ARM) • C code: g = h + A[8]; • g in r1, h in r2, base address of A in r3 • r5 is temporary register • Compiled ARM code: • Index 8 requires offset of 32 • 4 bytes per word LDR r5,[r3,#32] ; reg r5 gets A[8]ADD r1, r2, r5 ; g = h + A[8] base register offset Chapter 2 — Instructions: Language of the Computer — 22

  23. Memory Operand Example 2 (MIPS) • C code: A[12] = h + A[8]; • h in $s2, base address of A in $s3 • Compiled MIPS code: • Index 8 requires offset of 32 lw $t0, 32($s3) # load wordadd $t0, $s2, $t0sw $t0, 48($s3) # store word Chapter 2 — Instructions: Language of the Computer — 23

  24. Memory Operand Example 2 (ARM) • C code: A[12] = h + A[8]; • h in r2, base address of A in r3 • r5 is temporary register • Compiled ARM code: • Index 8 requires offset of 32 LDR r5,[r3,#32] ; reg r5 gets A[8]ADD r5, r2, r5 ; reg r5 gets h+A[8] STR r5,[r3,#48] ; Stores h+A[8]into A[12] Chapter 2 — Instructions: Language of the Computer — 24

  25. Instructions (MIPS) • Load and store instructions • Example: C code: A[12] = h + A[8]; MIPS code: lw $t0, 32($s3) ; $s3=A, 32=8*4 add $t0, $s2, $t0 sw $t0, 48($s3) • Store word has destination last • Remember: • Operands of arithmetic/logic instructions are registers, not memory! • Load/store instructions have one memory operand. • Note: • Temporary register: $t0; • Array name: a register $s3; • Displacement: 32, not 8! 48, not 12!

  26. Our First Example (MIPS) • Can we figure out the code? swap(int v[], int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; } swap: muli $2, $5, 4 add $2, $4, $2 ; $s2= addr.of v[k] lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 ; Return addr. is saved in $s31

  27. Our First Example (ARM) • Can we figure out the code? swap(int v[], int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; } swap: ; ARM assembly ADD r5, r0, r1, LSL #2 ; r5=addr. of v[k] ; r5 = r0 + r1<<2 ; r0 = v; r1 = k LDR r4, [r5, #0] ; r4 = v[k] LDR r6, [r5, #4] ; r6 = v[k+1] STR r6, [r5, #0] ; v[k] = r6 STR r4, [r5, #4] ; v[k=1] = r5 MOV pc, lr ; return to caller swap: ; MIPS assembly muli $2, $5, 4 add $2, $4, $2 ; $s2= addr.of v[k] lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 ; Return addr. is saved in $s31

  28. Registers vs. Memory • Registers are faster to access than memory • Operating on memory data requires loads and stores • More instructions to be executed • Compiler must use registers for variables as much as possible • Only spill to memory for less frequently used variables • Register optimization is important! Chapter 2 — Instructions: Language of the Computer — 28

  29. Immediate Operands (MIPS) • Constant data specified in an instruction addi $s3, $s3, 4 • No subtract immediate instruction • Just use a negative constant addi $s2, $s1, -1 • Design Principle 3: Make the common case fast • Small constants are common • Immediate operand avoids a load instruction Chapter 2 — Instructions: Language of the Computer — 29

  30. Immediate Operands (ARM) • Constant data specified in an instruction ADD r3,r3,#4 ; r3 = r3 + 4 • Design Principle 3: Make the common case fast • Small constants are common • Immediate operand avoids a load instruction Chapter 2 — Instructions: Language of the Computer — 30

  31. The Constant Zero • MIPS register 0 ($zero) is the constant 0 • Cannot be overwritten • Useful for common operations • E.g., move between registers add $t2, $s1, $zero Chapter 2 — Instructions: Language of the Computer — 31

  32. Unsigned Binary Integers • Given an n-bit number §2.4 Signed and Unsigned Numbers • Range: 0 to +2n – 1 • Example • 0000 0000 0000 0000 0000 0000 0000 10112= 0 + … + 1×23 + 0×22 +1×21 +1×20= 0 + … + 8 + 0 + 2 + 1 = 1110 • Using 32 bits • 0 to +4,294,967,295 Chapter 2 — Instructions: Language of the Computer — 32

  33. 2s-Complement Signed Integers • Given an n-bit number • Range: –2n – 1 to +2n – 1 – 1 • Example • 1111 1111 1111 1111 1111 1111 1111 11002= –1×231 + 1×230 + … + 1×22 +0×21 +0×20= –2,147,483,648 + 2,147,483,644 = –410 • Using 32 bits • –2,147,483,648 to +2,147,483,647 Chapter 2 — Instructions: Language of the Computer — 33

  34. 2s-Complement Signed Integers • Bit 31 is sign bit • 1 for negative numbers • 0 for non-negative numbers • –(–2n – 1) can’t be represented • Non-negative numbers have the same unsigned and 2s-complement representation • Some specific numbers • 0: 0000 0000 … 0000 • –1: 1111 1111 … 1111 • Most-negative: 1000 0000 … 0000 • Most-positive: 0111 1111 … 1111 Chapter 2 — Instructions: Language of the Computer — 34

  35. Signed Negation • Complement and add 1 • Complement means 1 → 0, 0 → 1 • Example: negate +2 • +2 = 0000 0000 … 00102 • –2 = 1111 1111 … 11012 + 1 = 1111 1111 … 11102 Chapter 2 — Instructions: Language of the Computer — 35

  36. Sign Extension (MIPS) • Representing a number using more bits • Preserve the numeric value • In MIPS instruction set • addi: extend immediate value • lb, lh: extend loaded byte/halfword • beq, bne: extend the displacement • Replicate the sign bit to the left • c.f. unsigned values: extend with 0s • Examples: 8-bit to 16-bit • +2: 0000 0010 => 0000 00000000 0010 • –2: 1111 1110 => 1111 11111111 1110 Chapter 2 — Instructions: Language of the Computer — 36

  37. Sign Extension (ARM) • Representing a number using more bits • Preserve the numeric value • In ARM instruction set • LDRSB,LDRSH: extend loaded byte/halfword • Replicate the sign bit to the left • c.f. unsigned values: extend with 0s • Examples: 8-bit to 16-bit • +2: 0000 0010 => 0000 00000000 0010 • –2: 1111 1110 => 1111 11111111 1110 Chapter 2 — Instructions: Language of the Computer — 37

  38. Representing Instructions (MIPS) • Instructions are encoded in binary • Called machine code • MIPS instructions • Encoded as 32-bit instruction words • Small number of formats encoding operation code (opcode), register numbers, … • Regularity! • Register numbers • $t0 – $t7 are reg’s 8 – 15 • $t8 – $t9 are reg’s 24 – 25 • $s0 – $s7 are reg’s 16 – 23 §2.5 Representing Instructions in the Computer Chapter 2 — Instructions: Language of the Computer — 38

  39. Representing Instructions (ARM) • Instructions are encoded in binary • Called machine code • ARM instructions • Encoded as 32-bit instruction words • Small number of formats encoding operation code (opcode), register numbers, … • Regularity! • Register numbers – r0 to r15 §2.5 Representing Instructions in the Computer Chapter 2 — Instructions: Language of the Computer — 39

  40. op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R-format Instructions (MIPS) • Instruction fields • op: operation code (opcode) • rs: first source register number • rt: second source register number • rd: destination register number • shamt: shift amount (00000 for now) • funct: function code (extends opcode) Chapter 2 — Instructions: Language of the Computer — 40

  41. op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R-format Example (MIPS) add $t0, $s1, $s2 special $s1 $s2 $t0 0 add 0 17 18 8 0 32 000000 10001 10010 01000 00000 100000 000000100011001001000000001000002 = 0232402016 Chapter 2 — Instructions: Language of the Computer — 41

  42. Cond F I Opcode S Rn Rd Operand2 4 bits 2 bits 1 bits 4 bits 1 bits 4 bits 4 bits 12 bits Data Processing (DP) Instructions (ARM) • Instruction fields • Opcode : Basic operation of the instruction • Rd: The destination register operand • Rn: The first register source operand • Operand2: The second source operand • I:Immediate. If I is 0, the second source operand is a register, else the second source is a 12-bit immediate. • S: Set Condition Code • Cond: Condition • F: Instruction Format. Chapter 2 — Instructions: Language of the Computer — 42

  43. Cond 14 0 F I 0 Opcode 4 S 0 Rn 1 Rd 5 Operand2 2 4 bits 4 bits 2 bits 2 bits 1 bits 1 bits 4 bits 4 bits 1 bits 1 bits 4 bits 4 bits 4 bits 4 bits 12 bits 12 bits DP Instruction Example (ARM) ADD r5,r1,r2 ; r5 = r1 + r2 111000001000000101010000000000102 Chapter 2 — Instructions: Language of the Computer — 43

  44. Machine Language: load/store instructions (MIPS) • Consider the load-word and store-word instructions, • What would the regularity principle have us do? • New principle: Good design demands a compromise • Introduce a new type of instruction format • I-type for data transfer instructions • other format was R-type for register • Example: lw $t0, 32($s2) 35 18 2 32 op rs rt 16 bit number • Where's the compromise?

  45. Machine Language PROBLEM: How to access an array element with displacement > 2^16? • Displacement > 2^16? X=A[100000]+……. Assume t1 is a temporary 32-bit register . m[1024] the memory location which has a large value. Its address is calculated by 0($s). t3 is a register contain the base address of array A. t4 is a temporary 32 bits register . lw $t1 , 0($s2); //load immediate to $t1. add $t4 , $t3 , $t1; //calculate the displacement. lw $t5 , 0($t4); //load the displacement to t5. t1 → ← m[1024] t3 → ﹜ Displacement>2^16 t5 → ← A[100000]

  46. Machine Language (corrected) PROBLEM: How to access an array element with displacement > 2^16? Displacement > 2^16? X=A[100000]+……. Assume t1 is a temporary 32-bit register . m[1024] the memory location which has a large value. Its address is calculated by 0($s). t3 is a register contain the base address of array A. t4 is a temporary 32 bits register . lw $t1 , 0($s2); //load immediate to $t1. add $t4 , $t3 , $t1; //calculate the displacement. lw $t5 , 0($t4); //load the displacement to t5. t1 → ← m[1024] t3 → ﹜ Displacement>2^16 t5 → ← A[100000]

  47. Hexadecimal • Base 16 • Compact representation of bit strings • 4 bits per hex digit • Example: eca8 6420 • 1110 1100 1010 1000 0110 0100 0010 0000 Chapter 2 — Instructions: Language of the Computer — 49

  48. op rs rt constant or address 6 bits 5 bits 5 bits 16 bits I-format Instructions (MIPS) • Immediate arithmetic and load/store instructions • rt: destination or source register number • Constant: –215 to +215 – 1 • Address: offset added to base address in rs • Design Principle 4: Good design demands good compromises • Different formats complicate decoding, but allow 32-bit instructions uniformly • Keep formats as similar as possible Chapter 2 — Instructions: Language of the Computer — 50

  49. Cond 14 F 1 24 Opcode Rn 3 5 Rd Offset12 32 4 bits 4 bits 2 bits 2 bits 6 bits 6 bits 4 bits 4 bits 4 bits 4 bits 12 bits 12 bits Data Transfer (DT) Instruction (ARM) • Design Principle 4: Good design demands good compromises • Different formats complicate decoding, but allow 32-bit instructions uniformly • Keep formats as similar as possible LDR r5, [r3, #32] ; Temporary reg r5 gets A[8] Chapter 2 — Instructions: Language of the Computer — 51

  50. Stored Program Computers • Instructions represented in binary, just like data • Instructions and data stored in memory • Programs can operate on programs • e.g., compilers, linkers, … • Binary compatibility allows compiled programs to work on different computers • Standardized ISAs The BIG Picture Chapter 2 — Instructions: Language of the Computer — 52

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