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Robust Window-based Multi-node Technology-Independent Logic Minimization. Jeff L.Cobb W Kanupriya Gulati D Sunil P. Khatri D. W Texas Instruments, Inc. D Dept. of ECE, Texas A&M University. Overview Introduction Background Previous work Approach Experimental results Conclusions.
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Robust Window-based Multi-node Technology-Independent Logic Minimization Jeff L.Cobb W Kanupriya Gulati D Sunil P. Khatri D W Texas Instruments, Inc. D Dept. of ECE, Texas A&M University
Overview Introduction Background Previous work Approach Experimental results Conclusions
Introduction VLSI design flow • HDL (Verilog, VHDL) • Logic optimization • Physical design
Introduction • Purpose of logic optimization • Reduce area • Reduce power • Reduce delay • Logic optimization • Technology-independent optimization • Goal: reduce literal count • Technology-dependent optimization
Background • Don’t Cares • Logic function allowed to have 0 or 1 as possible output for a given input ODC SDC • XDC: External don’t cares given
Background • Don’t Cares • Computed for one node at a time • Cannot capture multi-node flexibility xy (x+y) = xy(xy) + (x+y)(x+y) = xy+xy = x y • Goal: multi-node logic minimization • Yields a Boolean relation • Need to determinize this relation for solution
Background • Boolean relations • Can express more than one allowed output vector for a single input vector • Don’t cares only express flexibility for a single output
Problem Definition • Implement dual-node Boolean relation-based multi-level logic minimization technique • Goals: • Method must scale to large designs • Compare to best don’t care-based method (single-node)
Previous Work • [CM77] Formulated multi-node minimization problem • No results provided • [WW94] Multi-node minimization • Extremely large runtimes, works on very small designs • [MB05] Single node approach, uses windowing and SAT based formulation • Used for comparison purposes • This work: Efficient choice of nodes, window based, efficient quantification scheduling 10
Approach • Key features • Dual node optimization • Careful node pair selection • Window based optimization technique • Early quantification for efficiency
Node Pair Selection • Node Pair Selection
Node Pair Selection • Compute common input ratio • Compute common output ratio • Select node pairs that satisfy
Building the Relation • where
Endgame • Call BREL (a Boolean relation minimizer) to minimize • Returns new nodes and • Graft new nodes into • Delete original nodes • ,
BREL • BREL is a heuristic Boolean relation solver • Solving a Boolean relation • Same as minimum cost determinization of the relation (i.e. finding the lowest cost function which is contained in the relation) • Branch and bound approach
Experimental Results • Implemented in SIS • Uses CUDD ROBDD Package • 15 benchmark circuits from mcnc91, itc99 • Metric for quality: literal count • Preprocessing steps: • Removes constant-valued nodes • Removes nodes that do not fanout • Merges functionally identical nodes
Experimental Results • Parameter selection • 4 parameters to node selection algorithm • Goal: Find “golden” values
Experimental Results • Parameter:
Experimental Results • Parameters: • : Window size • : Partners for
Experimental Results • Parameter:
Experimental Results • “Golden” parameter values: • Can be modified to balance quality/runtime
Experimental Results • Compared versus • 12% lit. improvement • 38x runtime increase • But runtimes are • still within 3-4 min • Low memory (#BDD • nodes) • High gain (number of • node pairs which give • an improvement)
Experimental Results • Run after • 13% lit. improvement • Both use 2x2 windows
Experimental Results • Limit subnetwork size τ
Conclusions • 12% less literals than best DC approach • Runtimes under 4 minutes for largest network • Low memory usage • Further reduce literals by 13% after running best DC approach • Future Work • Consider 3+ nodes in relation • SAT-based relation construction • Alternative to BREL
