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A ROM-less DDFS Using A Nonlinear DAC With An Error Compensation Current Array

A ROM-less DDFS Using A Nonlinear DAC With An Error Compensation Current Array.

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A ROM-less DDFS Using A Nonlinear DAC With An Error Compensation Current Array

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  1. A ROM-less DDFS Using A Nonlinear DAC With An Error Compensation Current Array Chua-Chin Wang, Senior Member, IEEE, Chia-Hao Hsu, Student Member, IEEE, Tuo-Yu Yao, and Jian-Ming Huang, Student Member, IEEE Department of Electrical Engineering National Sun Yat-Sen University Kaohsiung, Taiwan 80424 Presenter：梁正勳 Number:97662003

  2. Outline • INTRODUCTION • THE PROPOSED DDFS DESIGN • SIMULATION AND IMPLEMENTATION • CONCLUSION

  3. INTRODUCTION • PLLs are usually employed to synthesize sinusoidal waves. • PLL based frequency synthesizers can not simultaneously provide both fast frequency switching and high spectral purity. • DDFS can provide faster frequency switching, excellent spectral purity,higher resolution,lower phase noise, and continuous phase frequency switching. • DDFS is capable of operating direct phase and frequency modulation in digital domain. • The ROM-based DDFS architecture demands a large ROM to store the sinusoidal amplitude data, which results in more power dissipation, slower speed, and poor spectral purity.

  4. Block diagram of the conventional DDFS Phase values are converted by the phase accumulator. Samples of the sinusoid amplitude generated by a ROM lookup table are passed to DAC. The sinusoid function is smoothed by LPF at last.

  5. THE PROPOSED DDFS DESIGN • Straight Line Approximation Fig. 2.The error between the real sinusoid and the synthesized one

  6. Proposed DDFS Architecture Fig. 3. The block of the proposed DDFS

  7. Nonlinear DAC Design Fig.4. The block of the proposed nonlinear DAC Fig.5. IAFC current mirror

  8. Differential-to-single voltage amplifier Fig.8. The differentia-to-single voltage amplifier

  9. SIMULATION AND IMPLEMENTATION Fig.10. The synthesized sine wave Fig.9. The layout of the proposed DDFS Fig.11. The spectrum of the synthesized sine wave

  10. Specifications and Comparison Table III shows the specifications and the comparison between the proposed design and the prior works.

  11. CONCLUSION • In this paper, a low power DDFS with error compensation is proposed. • This design using a nonlinear DAC is based on thestraight line approximation. • This technique transforms the conventional ROM-based phase conversion into one nonlinear DAC. • The power consumption as well as hardware complexity is greatly reduced without any loss of SFDR.

  12. The End Thank you for your attentions !

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