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5-Bit Current Steering DAC

5-Bit Current Steering DAC. Salih Kilic Jeff Lee James Li Brian Miller Advisor: Dave Parent May 17, 2004. Agenda. Abstract Introduction Why Simple Theory Back Ground information (Lit Review) Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions.

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5-Bit Current Steering DAC

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  1. 5-Bit Current Steering DAC Salih Kilic Jeff Lee James Li Brian Miller Advisor: Dave Parent May 17, 2004

  2. Agenda • Abstract • Introduction • Why • Simple Theory • Back Ground information (Lit Review) • Summary of Results • Project (Experimental) Details • Results • Cost Analysis • Conclusions

  3. Abstract • We designed a 5-Bit current steering DAC that operated at 150 MHz and occupied an area of 560 x 590mm^2

  4. Introduction • CMOS D/A converters have the advantage of low power, low cost, and are compatible with external CMOS circuitry. • CMOS D/A are essential components in most consumer video systems. • Create a current that is proportional to a digital input.

  5. Project Summary • Our DAC consisted of 3 blocks • Row/Column Decoder • D-Flip Flops • Current Cell Matrix

  6. Row/Column Decoder • We converted binary into thermometer code. • Ensures only 1 bit changes per state. • Multiple bits changing simultaneously causes BIG glitches! • Use of Row and Column keeps layout compact.

  7. Row/Column Decoder Schematics

  8. D-Flip Flops • Ensures synchronization of inputs • Prevents glitches

  9. D-Flip Flop

  10. Current Matrix • Decoding Logic • Decides which current cells to turn on. • Current Mirror • Mirrored 247.9um to 32 different current cells. • Current Switches • Linked our decoding logic to our current sources.

  11. Current Matrix Schematics

  12. Current, Voltage, Power • Average current: 6.3mA • Average Voltage: 2.5V • Area = 560um x 590um = 330,400um^2 • Power Density = (Iavg x Vavg)/Area = 4.76W/cm^2

  13. Longest Path Calculations Note: All widths are in microns and capacitances in fF

  14. Schematic

  15. Layout

  16. Verification

  17. Simulations

  18. Cost Analysis • Estimate how much time you spent on each phase of the project • verifying logic : 2 weeks • verifying timing : 3 weeks • layout : 2 week

  19. Lessons Learned • Don’t route in poly • Make Flip Flop layout compact • Start Early • Go to office hours

  20. Summary • Our DAC functions at 150MHz and occupies an area of 560um by 590 um with power density of 4.76W/cm^2. • Future DAC’s will be more compact and able to function at higher frequencies with less power consumption

  21. Acknowledgements • Thanks to Dr. Parent for direction and guidance • Thanks to Cadence Design Systems for the VLSI lab • Thanks to Synopsys for Software donation

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