Development of novel n + -in-p Silicon Planar Pixel Sensors for HL-LHC

1. Development of novel n+-in-p Silicon Planar Pixel Sensors for HL-LHC Y. Unnoa, J. Idarraga1, S. Mitsuia, R. Horia, R. Nagaig, O. Jinnouchig, A. Lounis1, Y. Takahashih , K. Harah, S. Kamadab, K. Yamamurab, A. Ishidab, M. Ishiharab, T. Inuzukab , Y. Ikegamia, T. Kondoa, Y. Takuboa, S. Teradaa, J. Tojoa, R. Takashimac, I. Nakanod , K. Hanagakie, N. Kimurai, K. Yoritai aHigh Energy Accelerator Research Organization (KEK) and The Graduate University for Advanced Studies (SOKENDAI) bHamamatsu Photonics K.K. cDepartment of Education, Kyoto University of Education dDepartment of Physics, Okayama Univeristy eDepartment of Physics, Osaka University fUniversite de Paris-Sud 11 gDepartment of Physics, Tokyo Institute of Technology hInstitute of Pure and Applied Sciences, Univeristy of Tsukuba iResearch Institute for Science and Engineering, Waseda University Y.Unno, HSTD8, 2011/12/6

2. Introduction • Planar pixel sensor aiming for very high radiation environment, such as high-luminosity LHC • 1015 – a few x 1016 neq/cm2 • n-in-p benefits • No type inversion after irradiation • Single side lithographic process • Low cost • Readout from n+ of p-n junction • Possible partial depletion operation • In all circumstances • Readout in higher electric field • Stronger induction current • Collecting electrons • Faster carrier, less trapping • n-in-p strips were reported in the last symposium (HSTD7) • Y. Unno et al., Nucl. Instr. Meth. A 636, Supplement, 21 April 2011, Pages S24-S30, and other 3 papers in the issue. Y.Unno, HSTD8, 2011/12/6

3. n-in-p pixel issues • n-in-p issues • Isolation of n+ pixels • HV protection at the diced edge • Issues in planar pixel sensor in general • HV operation capability • Up to 1000 V, e.g., to cope with radiation damage in bulk • Material reduction • Thin sensor • Inefficient area due to “bias” structure • required for testing all pixels, with I-V performance, e.g. • Bump bonding • limited number of vendors • Content of the talk • Pixel structures • Biasing x Isolation • Thin sensor • HV protection • Bump-bonding Y.Unno, HSTD8, 2011/12/6

4. Novel n-in-p HPK Pixel Sensors FE-I3 (~1cm□) FE-I4 (~2cm□) • n-in-p 6-in. wafer process in HPK • ATLAS FE-I3 and FE-I4 pixel sensors • Biasing: Punth-thru (PT) dot at 4-corner or PolySi resister • Isolation: p-stop (common, individual) or p-spray • “Bias rail” is a metal over insulator, no implant underneath. No electrode in the silicon, other than the bias “dot” • Thinning • Finishing 320 µm wafer process first • Thinning the wafers to 150 µm • Completing the backside FE-I3 1-chip pixels PTLA Isolation scheme Bias rail FE-I4 2-chip pixels Biasing Scheme FE-I4 1-chip pixels PolySi FE-I3 4-chip pixels HPK n-in-p 6-in. wafer Y.Unno, HSTD8, 2011/12/6

5. Thin n-in-p HPK Pixel Sensors • I-V performance (before UBM and dicing) • All (-most) were good up to 1000 V • p-spray sensors break around 900 V, still good • After bump-bonding • 4 out of 4 were all good up to 1000 V • 16 wafers are processed • 150 µm thick • 4 wafers were sent for UBM+Bumpbonding. • Measured data of the 3 wafers of p-stop: • 18 FE-I4 1-chips • 18 FE-I4 2 –chips • 21 FE-I3 1-chips • 9 FE-I3 4-chips 1 µA FE-I4 2-chip FE-I4 1-chip, FE-I3 4-chip FE-I3 1-chip Y.Unno, HSTD8, 2011/12/6

6. Before/After irradiation No charge mult. yet… • Results from test beams • 2x1015 neq/cm2 • See the poster by R. Nagai et al. • Slim edge, multi guard • 5x1012 – 5x1015 neq/cm2 • See the poster by S. Mitsui et al. 99.8% 99.2% 2D efficiency map of one pixel, non-irrad, at 150 V bias voltage 99.8% 94.1% #5 #6 #3 #4 1 8 [μm] 6 Arbitrary unit 4 2 0 8 6 4 2 0 [μm] p-stop individual, PTLA p-stop common, Poly-Si p-stop individual, Poly-Si p-stop common, Poly-Si Depth (mm) Shallow incident angle analysis Y.Unno, HSTD8, 2011/12/6 black : avg. non-irradiated red : avg. irradiated (2x1015) Q [e] (Arbitrary unit) Bias voltage [V] Bias voltage dependence of collected charges Note: independent charge calibration for non-irradiated and irradiated samples.

7. HV protection – Low-tech solutions • Real pixel sensor (FE-I3) + dummy chip (Al traces) • bump-bonded • Three types of encapsulation • Encapsulation material – Silicone adhesive (soft) • No encapsulation (#1), X-points (#2), full line (#3) Weak cross points 1. Encapsulation #2: Encapsulation of x-points #3: Full line encapsulation #1: No encapsulation Y.Unno, HSTD8, 2011/12/6

8. Encapsulation – Spark test • Spark occurs • ~500 V at X-points without protection • good info. • ~700 V at Al-traces facing to the sensor edge • No open/no passivated trace in the real FE-I4 chips (?) • No spark up to 1000 V with full encapsulation • We have at least a candidate to protect the edge. Spark location Spark location #2: Spark location – Al trace ~690 V #1: Spark location – X-points ~500 V #3: No spark up to 1000 V Y.Unno, HSTD8, 2011/12/6

9. Encapsulation – FE-I4’s testbeam • Post-process application • Silicon adhesive • Both non-irradiated and irradiated single chip modules (SCM) • successfully operated up to 1000 V in the testbeam Y.Unno, HSTD8, 2011/12/6

10. HV protection – 2. Parylene coating • Parylene coating • Two FE-I3 SCMs • After wire-bonding • Covering all over • Parylene C, ~3 µm • Softer Parylene-N might be better (?) • I-V measurement • Shorted ~700 V • Consistent with known shorts in the single chip card Parylene coating (C: ~3 µm) 1.1x1015 1-MeV neq/cm2 -25 °C, No LV power FE-I3 module FE-I4 single chip card Coated area Y.Unno, HSTD8, 2011/12/6

11. Bump-bonding at HPK • IZM • Well-established through current pixel detectors at LHC • PbSn solder bumps – old fashioned • HPK dummy chips + IZM UBM+PbSn bumps • FE-I3 HPK sensor + FE-I3 chips (with IZM PbSn bumps) • Testbeam in Oct. 2010 • Irradiation in Feb. 2011 • SnAg (Pb-free) bumps (by HPK) - current industry standard • HPK dummy chips + HPK UBM + SnAg bumps • 320 µm and 150 µm • FE-I3 and FE-I4 types • Singles and “4-chip”s • Irradiation and testbeams in 2011 • Establishing the technology at HPK • Benefits in doing at the sensor vendor • Faster and invaluable internal feedback • both in the bump-bonding and sensor fabrication Y.Unno, HSTD8, 2011/12/6

12. PbSn Bump-bonding at HPK • Al-pattern with bumps • Pb (PbSn) and Pb-free (SnAg) solder • FE-I3 and FE-I4 pattern • Single chips • Multi-chips next • Results • Good peel strength • Good yield of bump connection • ~0.14 Ω/bump resistance FE-I4 FE-I3 FE-I4 Dummy FC ~0.14 Ω/bump Differential Resistance (Ω) Differential Resistance per 2 rows (Ω) Resistance Number of bumps (FE-I4 type) Y.Unno, HSTD8, 2011/12/6

13. SnAg Bumpbonding at HPK 150 µm thick FE-I4 single chip daisy-chain sample • Latest achievement • FE-I4 single chip • 150 µm thickness both • ~0.28 Ω/bump • 4-chip trials • with dummy sensor & chips • both 320 µm thick • Pb-free (SnAg) bumps 4-chip module Integral Resistance (Ω) Resistance per 2-rows (Ω) Number of bumps Y.Unno, HSTD8, 2011/12/6

14. Thermal cycling • Low (-40 °C) and High (+50 °C) Climate chambers, each with a large aluminum block for a thermal capacitor • Samples were laid on an aluminum box. A pt100 resistor was also attached on a silicon piece. • Temperature of the pt100 was read out with a Keithley 2700 multimeter • The aluminum box was placed on the aluminum block for 30 min. • Transfer the sample box by hand High temp. Climate Ch. Low temp. Climate Ch. Pt100 Transfer sample sample sample Pt100 Pt100 Alumi block Alumi block Alumi box Y.Unno, HSTD8, 2011/12/6

15. Results of FE-I4 single chip dummies • Temperature slope upward • First 30 s, first 1 min. averages • 54.09K/30s、73.43K/min • Temperature slope downward • -57.70K/30s、-71.58K/min • ~70 K/min thermal shock was achieved • Consistent resistances before/after thermal cycling of 10 time • 1st-last pad resistance • All 6 samples has survived. Temperature reading per 10 s ℃ h Y.Unno, HSTD8, 2011/12/6

16. Summary • Thin FE-I3 and FE-I4 pixel sensors were successfully processed, with novel biasing and isolation schemes. • FE-I4 thin pixel 1-chip SCMs, bump-bonded at IZM, were evaluated through a chain of testbeam, irradiation, and testbeam. • Results for the biasing and isolation performance comparison are in hand. • Polysilicon biasing with common p-stop isolation performs best. • Low-tech solution of HV protection has been tried out with • Parylene coating and encapsulation • Both were successfully preventing HV shorts, up to 1000 V. • SnAg bump-bonding at HPK are being established. • Chip thickness of 150 µm and 320 µm • Dummies have survived after 10 time of thermal cycling with the temperature slope of ~70 K/min. Y.Unno, HSTD8, 2011/12/6

17. Backup Y.Unno, HSTD8, 2011/12/6

18. Features in HPK n-in-p Sensors • Bias structures • Reducing less-efficient area • PTLA (a bias-dot in the 4-corner) • PolySilicon (encircling pixel implant) • Isolation structures • p-stop (~4x1012 cm-2) • Common • Individual • p-spray (~2x1012 cm-2) PTLA Isolation scheme Bias rail Biasing Scheme PolySi • “Bias rail” is a metal over insulator, no implant underneath • No electrode in the silicon, other than the bias “dot” Y.Unno, HSTD8, 2011/12/6

19. HPK thin pixel sensor FE-I4 SCM’s • 4 HPK thin sensors were bump-bonded at IZM. • Delivered to Univ. Bonn and waiting for mounting to the boards. • Characterization and testbeam • Initial characterization will be carried out at Bonn. • Further characterization in Japan, in June • Looking forward to the testbeam at CERN in July (and Sep.) • Irradiation (at Karlsruhe(?)) at a time of July-Sep.(?) Y.Unno, HSTD8, 2011/12/6