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VHDL Source Code for eP32

VHDL Source Code for eP32. 2012 FIG Taiwan Conference February 17, 2012 Chen-Hanson Ting. Summary. ep32_chip.vhd Overall Design ep32.vhd CPU of eP32 ram_memory.vhd Memory of eP32 uart.vhd Serial port gpio.vhd General purpose IO ep32q_tb.vhd Testbench. VHDL Souce code.

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VHDL Source Code for eP32

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  1. VHDL Source Code for eP32 2012 FIG Taiwan Conference February 17, 2012 Chen-Hanson Ting

  2. Summary • ep32_chip.vhd Overall Design • ep32.vhd CPU of eP32 • ram_memory.vhd Memory of eP32 • uart.vhd Serial port • gpio.vhd General purpose IO • ep32q_tb.vhd Testbench

  3. VHDL Souce code • I will scan the source code files so we have a general idea on what eP32 contains and how it is implemented. • VHDL code is very portable so that you can move it to any FPGA chip or ASIC chip. • eP32 is the simplest, yet most complete microprocessor design ever.

  4. ep32_chip.vhd • Define all external connections • Define ports of all components • Define signals connecting all components • Instantiate all components

  5. ep32.vhd • Define IO ports of CPU • Define internal signals and registers • Define logic relations among signals • Define instruction set • Define finite state machine to execute instructions

  6. ram_memory.vhd • Instantiate DQ RAM memory modules. • Initialize RAM memory contents to a FORTH dictionary. • This module cannot be ported from one FPGA to another. It must be generated by tools provided by specific FPGA IDE. • eP32 requires asynchronous RAM modules. • Memory is mapped to 0-$00001FFF.

  7. uart.vhd • Instantiate a Universal Asynchronous Receiver Transmitter (USART). • USART is initialized to 115,200 baud, 1 start bit, 8 data bits, 1 stop bit, no parity, and no flow control. It can be configures to other options. • USART registers are mapped to $8000000x.

  8. gpio.vhd • Instantiate a 16 bit general purpose IO port. • It includes these registers: • Direction Register • Input Register • Output Register • Registers are mapped to $E000000x.

  9. ep32q_tb.vhd • It is required by ispLEVEL to simulate eP32 chip. • A template is provided by ispLEVEL. It is customized for eP32 chip. • DIAMOND does not need a testbench. Signals in the eP32_chip top module can be customized to drive eP32 chip.

  10. Conclusion • CPU design is simple. • Most CPU designers do not understand computer, and made their designs unnecessarily complicated. • eP32 is the simplest, yet most complete microprocessor design ever.

  11. 莊子『庖丁解牛』 良庖歲更刀，割也。 族庖月更刀，折也。 今臣之刀十九年矣，所解數千牛矣，而刀 刃若新發於硎。 彼節者有閒，而刀刃者無厚，以無厚入有 閒，恢恢乎其於遊刃必有餘地矣。

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