1 / 14

Understanding Cache Hierarchy Interactions using a Program-Driven Simulator

Understanding Cache Hierarchy Interactions using a Program-Driven Simulator . Julio Sahuquillo , José Flich Computer Engineering Department Technical School of Applied Computer Science Technical University of Valencia. Leticia Pascual, Alejandro Torrentí Instituto Tecnológico de Informática

vonda
Download Presentation

Understanding Cache Hierarchy Interactions using a Program-Driven Simulator

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Understanding Cache Hierarchy Interactions using a Program-Driven Simulator Julio Sahuquillo, José Flich Computer Engineering Department Technical School of Applied Computer Science Technical University of Valencia Leticia Pascual, Alejandro Torrentí Instituto Tecnológico de Informática Technical University of Valencia

  2. Outline • 1. Cache memories • 2. Tools used in the Academia • 3. PC-spim cache • 4. Proposed tool: Spim-Vista • 5. Working example • 6. Conclusions

  3. Cachememories • Memory speed is two order of magnitude higher than microprocessor core speed • Cache memories: mechanism to hide these latencies • Current microprocessors include several cache levels • Main uses • High performance processors, mobile devices, phone cells, etc • Teaching • Understanding how caches work is essential to understand how processors work • Identified as core topic in those disciplines offering Computer Organization/Architecture courses • Computer engineering, electrical engineering, telecommunication engineering, …

  4. Cachememories: a wide range of concepts • Computer Organization Course: second year • Basis of caches • How to find a block? Mapping functions • Replacement algorithms • Write hit policies: write through and write back • Write miss policies: write allocate and write no allocate • Computer Architecture Course • Advanced concepts • Victim caches • Coherence • Trace Cache •  simulators and laboratories can help

  5. Simulation tools used in the Academia • Two main groups • Trace driven • (+) Easy to understand, ex., Dinero IV • Mainly used for teaching purposes • Execution or program driven • More complex, ex. Simplescalar • (+) Provide a view of the system working as a whole • Mainly used for researching purposes • Tradeoff for instructors • Design simple program driven simulators to undergraduates

  6. PC-spim cache [WCAE 2006] • Program driven simulator • Extends PC-spim • PC-spim simulates MIPS assembly language • First temptative dealing with code based exercises • Why we extended PC-spim? Because students know MIPS language • What are code based exercises? • Simple algorithms implemented in a given language to study cache accesses • Typically used by instructors at classroom • This exercise can help to study mapping functions or spatial locality sum = 0; for (i=0; i<100; i++) sum = sum + A[i]

  7. Code based exercise: details • Example: sum of the elements of an Array • Examples of exercises • For a given cache geometry, obtain the sets in which Array_A map to, assuming that a is stored in address 0x10001000 • Number of misses and classify them according to the three C’s

  8. PC-spim cache [WCAE 2006] • Main limitations from the pedagogical point of view • There is no cache hierarchy • Cache interactions cannot be studied • Design Interface • Fully integrated following the PC-spim design • Homogeneous design but little practical

  9. Proposal: Spim-Vista • Main issues (1/2) • Extends PC-spim • Cache hierarchy • Two levels of caches • Caches are independently configured • You can observe different events (hit, miss or no action) at L1 and L2 • You can study how different cache levels impact on performance

  10. Proposal: Spim-Vista • Main issues (2/2) • User friendly interface based in colors • Different colors mean different events: e.g., cache miss, cache hit • If desired you can hide data information • You don’t need to know the block contents when studying the hit ratio • Permits to hide non-accessed cache blocs • Interesting when simulating large caches • Statistical information is shown for each cache, so providing support for performance studies (i.e., hit ratios)

  11. Working example STEPS • 1. Enable cache simulation • 2. Configure caches • 3. Load the program • 4. Run the program • Step by step • All the program at once • Let us run SpimVista to see its features

  12. Conclusions • Spim-Vista extends PCSpim to work with cache memories • Permits to perform code based exercises • Spim-Vista provides support to study cache hierarchy • Allows to evaluate different cache hierarchy configurations • It is currently being used at laboratory by students of the Technical University of Valencia • Assuming fixed L1, L2, and MM times, simple performance evaluation studies can be done • Future versions will cover timing issues • Early restart, critical word first, blocking caches, etc, • Send an email to me at jsahuqui@disca.upv.es to get a copy of the tool

  13. Thank you very much for your attention

  14. Understanding Cache Hierarchy Interactions using a Program-Driven Simulator Julio Sahuquillo, José Flich Computer Engineering Department Technical School of Applied Computer Science Technical University of Valencia Leticia Pascual, Alejandro Torrentí Instituto Tecnológico de Informática Technical University of Valencia

More Related