Enabling the ARM Learning in INDIA

1. LPC2148 System Peripherals Enabling the ARM Learning in INDIA

2. TOOL SETUP • AGENDA • Bus Structure • Memory Map • Memory Accelerator Module • Boot Loader • ISP & IAP • PLL • VLSI Peripheral Bus Driver • Power Control • Interrupt System Enabling the ARM Learning in INDIA

3. Bus Structure • In LPC2148 three types of busses are used to connect the core with other peripherals on chip. • Local Bus to connect the onchip memory controllers and fast GPIO’s • AMBA Advance High Performance Bus (AHB) for interrupt controller • VLSI Peripheral Bus (VPB) for other onchip peripherals. • AHB acts as a bridge for VPB. • VPB is mainly meant for connect slower peripherals then that of processor. • VPB can dive the peripherals at ¼ CPU clock frequency. Enabling the ARM Learning in INDIA

4. Bus Structure Enabling the ARM Learning in INDIA

5. Memory MAP To access any peripheral we need its address. The entire address space can be divided in to several sections. Enabling the ARM Learning in INDIA

6. Memory MAP Enabling the ARM Learning in INDIA

7. Memory Access Module The MAM block in the LPC2148 maximizes the performance of the ARM processor when it is running code in Flash memory, Two general methods for achieving code execution performance. Using RAM for code execution. Using Cache memory. Enabling the ARM Learning in INDIA

8. Memory Access Module The MAM block in the LPC2148 Enabling the ARM Learning in INDIA

9. Bootloader A small piece of software executed after every reset. This software is used to load the new user program in to the flash memory using any communication channel like UART, USB, Ethernet or CAN. For LPC2000 Series the Bootlader can be activated by maintaining low level on P0.14 while reset. Enabling the ARM Learning in INDIA

10. Bootloader ISP Philips microcontroller have a great feature called ISP (In System Programming). It enables the user to flash the microcontroller with an ease. In LPC2148 the ISP mode can be activated by maintaining low level on P0.14 while reset. Enabling the ARM Learning in INDIA

11. Boot Process Enabling the ARM Learning in INDIA

12. ISP Commands Enabling the ARM Learning in INDIA

13. IAP In-Application (IAP) programming is performing erase and write operation on the on-chip flash memory, as directed by the end-user application code. The bootloader code provides API to access flash memory from the user program. The API are called using their codes. Enabling the ARM Learning in INDIA

14. Phased Lock Loop Fout Mul Fin Div Basic PLL Block Diagram PLL is a closed loop control system to generate high frequency by multiplying with given factor to the input frequency. In LPC2148 microcontrollers there are 2 PLLs which provides programmable frequencies to the CPU and USB system. The input clock frequency to PLL0 and PLL1 is in the range of 10MHz to 25 MHz only. It is multiplied up the range of 10MHz to 60MHz for CCLK and 48MHz for the USB cock using Current Controlled Oscillator (CCO). Enabling the ARM Learning in INDIA

15. PLL Programming PLL Registers Detail Register Bits LPC214X User Manual Page 27 Enabling the ARM Learning in INDIA

16. PLL Programming • Programming Steps: • Select the desired operating frequency for your system ( Processor operating • frequency) CCLK. • Check the oscillator connected to the controller on board. (FOSC) • Calculate the value of PLL multiplier “M”. CCLK = M × FOSC • Find the value of PLL Divider “P” in such a way that is in the range of 156 MHz • to 320 MHz. 156 < FCCO < 320 = CCLK x 2 x P • Write the values PLLCON and PLLCFG. • Write the PLLFEED Values 0xAA and 0x55. • Wait for PLL to lock. • Connect the PLL. Enabling the ARM Learning in INDIA

17. VBP Divider VLSI Bus connected to various peripherals can be operated at different speeds using the VBP Divider. The VPB Divider serves two purposes: 1. Provides peripherals with desired PCLK via VPB bus, the VPB bus may be slowed down to one half or one fourth of the processor clock rate 2. VPB Divider allow power savings when an application does not require any peripherals to run at the full processor rate. Enabling the ARM Learning in INDIA

18. VBP Divider • VPBDIV registers least 2 significant bits can be changed for desired PCLK • Peripherals on LPC2000 series can run at the full 60 MHz clock. Enabling the ARM Learning in INDIA

19. POWER CONTROL LPC214x support two reduced power modes Idle mode and Power-down mode. Idle Mode: The CPU stops execution is suspended until a Reset or Interrupt from peripheral occurs. Peripheral runs in idle mode and may generate interrupts to resume the CPU execution. Power-Down Mode: The oscillator is shutdown and the chip receives no internal clocks. All the information of current execution state is preserved in this mode. A Reset signal or External Interrupt can terminate the power-down mode. PCON Register: Bit 0 : When set to 1, causes the processor clock to be stopped. Bit 1 : When set to 1, causes the on-chip clock to be stopped. In LPC214x the power down mode have dependency on USB Block Enabling the ARM Learning in INDIA

20. Peripheral Power Control • LPC2000 peripherals can be turned of individually using the PCONP Register bits setting, • to save the power. • Few peripherals like GPIO, Watchdog timer, Pin connect block and System Control block • cannot be turned off. • After reset the PCONP contains the value to enable all peripherals, so no need to • configure PCONP bits in-order to use any peripheral. • Page 37 LPC2148 User Manual Enabling the ARM Learning in INDIA

21. INTERRUPT SYSTEM Interrupt System • ARM PrimeCell™ Vectored Interrupt Controller • 32 interrupt request inputs • 16 vectored IRQ interrupts • 16 priority levels dynamically assigned to interrupt requests • Software interrupt generation Enabling the ARM Learning in INDIA

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