Performed by: Yulia Turovski Lior Bar Lev Instructor: Mony Orbach

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Final Presentation I Subject: High-Speed Communication Channel(s) Switch Performed by: Yulia Turovski Lior Bar Lev Instructor: Mony Orbach Winter semester 2010 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Outline • Reminder – Motivation and Goal • Stratix II SI Development Kit • Project Basics • Reminder - Architecture and Components • Validation Method • Synthesis Problems 2

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Motivation and Goal • Motivation: • High-speed communication between devices. • Utilizing high frequency achievable with new hardware. • Demand for reliable communication • Goal: • Design & implementation of high speed communication switch. • Use of advanced communication protocols. • Connect between as many devices as possible. • Best transmission rate possible. 2

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Stratix II SI Development Kit • The hardware for the project: Stratix II GX Transceiver Signal Integrity Development Board • Clocking: Numerous oscillators, we chose PCI-Express standard 156.25 MHz. • Communication channels: • 4 identical stripline channels - USED • 2 unique channels (microstrip and long trace simulator) – not used • Stratix II GX EP2SGX90EF1152C3 FPGA – 90,960 LE’s, Max Transceiver data rate 6.375Gbps, 4,520K RAM, 192 18X18 Multipliers, 48 DSP blocks, 8 PLLs, 558 I/O pins 2

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Stratix II SI Development Kit 2

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Project Basics • Communication using board’s transceivers. • Basic element: ALT2GXB MegaCore: • Receiver-transmitter from transfer size (32bit max for 1 lane) to serial interface. • Multiplies core clock to reach desired data rate • Tested thoroughly in previous project • Successfully burnt and tested • Alternative: SerialLite II MegaCore: • Uses ALT2GXB as a component • Adds optional data link services i.e. reliability, CRC, flow control etc. 2

7. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Architecture Diagram ROUTER 128 128 128 ALTGX ALTGX ALTGX TRNS TRNS TRNS OUTBUF OUTBUF OUTBUF 32 32 32 128 ALTGX TRNS OUTBUF 32 INBUF INBUF INBUF INBUF 32 RECV 128 SPLIT INBUF 32 32 32 RECV RECV RECV SPLIT SPLIT SPLIT 128 128 128 INBUF Trans Mem INBUF INBUF INBUF INBUF INBUF INBUF INBUF Trans Mem Trans Mem Trans Mem INBUF INBUF INBUF 3

8. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Architecture Diagram ROUTER 128 ALTGX TRNS OUTBUF 32 INBUF 32 RECV 128 SPLIT INBUF INBUF Trans Mem INBUF 3

9. From Simulation to Validation • Code incompatibility (Case) • Physical layer limitations • Previously checked at 0.6Gbps, 8-bit • Solution: • BYTESEP unit • BYTEMRG unit • 16 bit, then back to 8 bit • Multiple clock zones

10. Synthesis Stages • ALTGX check • Loopback: Output Mem -> Input Mem • Max bandwidth – 16 bits • Max frequency – 2.5 Gbps • Receiver – Transmitter • Loopback: From and to synthesizable testbench • Max bandwidth – 16 bits (with problems) • Max frequency – 1.5 Gbps • Full switch on FPGA + RT Testbenches • Loopback through switch • Frequency set to 0.6 Gbps • Bandwidth reduced to 8 bits

11. Issues Worked Out • ALTGX Problems • Clock domains • Receiver, transmitter • 8-bit, 32 bit (X4) • Core clock • Counters between clock domains • Opencore Plus limitations (CRC blocks) • DIP buttons -> PUSH buttons • Inter-board malfunctions • Probably still some bugs

12. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Validation Method • 2 transmitters with pre-initialized dual port rams • Simple data validation control (to keep track of number of packets sent) • A few scenarios were implemented - • Measure latency • CRC code detection • Latency is 264 clock cycles = 1.6896 usec • Measure Throughput • Parallel transmission • Output the data through In-Mem interface • Process: force reset down and up, examine output mem. 8

13. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Under Test Test device Switch Port I Port I Out Mem RT Testbench TRNS RECV Port II Port II Out Mem TRNS RT Testbench RECV Port III Port III TRNS Out Mem RT Testbench RECV Port IV Port IV RT Testbench TRNS Out Mem RECV 2

14. <picture of the system>

15. Summary • Fixed width, fair and reliable switch • (with some bugs?) • Dependant on the physical interface • Most of Part II – dealing with its limitations • Proof of success • Inconsistent results – with reducing likelihood: • ALTGX bugs • Intermediary bugs • Maybe some switch bugs • Unresolved – problem on two boards • If in the future a 32 bit physical interface will be possible – the switch should perform adequately.