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Chapter 11 Analog I/O Interfacing

Chapter 11 Analog I/O Interfacing. From Introduction to Embedded Systems by Valvano. 11.1 Approximating Continuout Signals in the Digital Domain. Analog Signal —one that is continuous in both amplitude and time. To “digitize” the signal, it is quantized in amplitude and time.

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Chapter 11 Analog I/O Interfacing

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  1. Chapter 11 Analog I/O Interfacing From Introduction to Embedded Systems by Valvano

  2. 11.1 Approximating Continuout Signals in the Digital Domain • Analog Signal —one that is continuous in both amplitude and time. • To “digitize” the signal, it is quantized in amplitude and time. • Limits are placed in the amplitude (0 to 5 volts) • The amplitude may be divided into a finite set of discrete values.

  3. 11.1 (cont.) • Range of system —maximum minus minimum. • Precision of system– defines the number of values from which the value is selected. • Resolution – is the smallest change in value that is significant.

  4. Figure 11.1 • Fig. 11.1 is a temperature waveform Fig. 11.1 is a temperature waveform. • 0-32 degrees (C) • 5 bits used for the amplitude. • 1 Hz sampling speed (periodic interrupt).

  5. Figure 11.1 (cont.) • Nyquist Rate—sample at twice the highest frequency or aliasing will occur.

  6. Checkpoint 11.1 • Why can’t the digital samples represent the little wiggles in the analog signal? • ANSWER—because the frequency components of the wiggles are higher than half the sample rate. Thus, the Nyquist Theorem is violated.

  7. Checkpoint 11.2 • Why can’t the digital samples represent terperatures above 31 degrees? • Answer: Because temperatures above 31 degrees are beyond the range, which is defined in this example as (0-31).

  8. Figure 11.2 • Shows DAC and ADC. • For the 9S12, the SPI can be used for interfacing. • Assume we have an m-bit DAC. • Assume N is an m-bit digital output of the microcomputer. • Vout = (Vmax-Vmin)* N/2m + Vmin.

  9. Designing a DAC • Example 11.1 –design a 2 bit DAC • Table 11.1 show the specifications. • Figure 11.3 illustrates a 2 bit DAC. • Checkpoint 11.3—How would you design a 3-bit DAC, using this method? (use resistors with a 1/2/4 ratio.)

  10. 11.3 Music Generation • Figure 11.4—illustrates interface to headphones, and an audio amplifier connected to a speaker. • Figure 11.5—loudness (amplitude) and pitch (1/period). • Table 11.2—frequencies of musical notes. • Page 402 has more information.

  11. 11.4 Analog to Digital Conversion • Most of the 9S12 microcontrollers have a built-in ADC • Table 11.3, page 404. • 9S12C32—1 8 channel 10-bit ADC –Port AD bit 7-0. • 9S12DP512—two 8-channel 10 bit ADC.

  12. 11.4.1 9S12 ADC Details • 9S12C32 • Port AD can be individually defined as analog input, digital output, or digital input. • Set the corresponding bit in the DDRAD register to 1, then that bit can be used as a digital output.

  13. ADC • When triggered, the ADC performs a sequence of conversions, with the sequence length being any number from 1 to 8 conversions. • Table 11.3 lists the registers used for ADCs.

  14. Table 11.3 • ATDCTL2—control register 2—bits that activate the ADC module. • ADPU—bit 7 --enables when 1 • AFFC—bit 6 • AWAI – bit 5 • ETRIGLE—bit 4 –External Trigger Mode bit • ETRIGP—bit 3—used with ext. trigger mode • ETRIG—bit 2—used with ext. trig.mode (T11.4) • ASCIE –bit 1—will request interrupt on completion • ASCIF—bit 0—ATD Sequence Complete Interrupt Flag.

  15. Table 11.3 • ATDCTL3—control register 3—bits that configure the ADC mode. • Bit 7—0 • Bit 6—S8C (sequence conversions) • Bit 5– S4C • Bit 4– S2C • Bit 3—S1C • Bit 2—FIFO—(not in text—freeze mode) • Bit 1 – FRZ1 • Bit 0– FRZ0

  16. Table 11.3 • ATDCTL4—control register 4—more bits that configure the ADC mode. • Bit 7—SRES8—resolution select bit • Bit 6—SMP1—sample time select bit • Bit 5—SMP0– sample time select bit. • Bit 4– PRS4 • Bit 3—PRS3 • Bit 2—PRS2 • Bit 1– PRS1 • Bit 0—PRS0

  17. Table 11.3 • ATDCTL5—writing to this register starts and ADC conversion • Bit 7-- DJM—Result register data justified bit. • Bit 6– DSGN—Data representation bit. • Bit 5– SCAN– related to no. of sequences • Bit 4—MULT—multiple possible input bits. • Bit 3—0 • Bit 2—CC2—sequence counter (with bit 1 & 0) • Bit 1—CC1 • Bit 0—CC0

  18. Table 11.3 • Other registers • ATDSTAT0 • ATDSTAT1 • ATDDIEN • PORTAD—(PAD7—PAD0) • ATDDR0-7—Results of the conversions.

  19. ADC Triggers • Three ways to trigger the ADC • (1)Use an explicit software trigger—when conversion is complete, the SCF flag is set • (2)continuous mode—software starts, but the sample sequence is repeated continuously. • (3) external trigger on digital input, PAD07. • The results are found in ATDDRs.

  20. Number of Conversions • Bits S8C, S4C, S2C, S1C control the number of conversions per sequence. • Let n be the four bit number indicated. • For n equals 1-7, n will be the length. • For n=0, or 8 – 15, the length is 8. • SRES8—the ADC resolution select bit • 8 bits when SRES8 = 1 • 10 bit when SRES8 = 0

  21. Timing • 8-bit resolution reduces conversion time and may reduce software design. • 10 microseconds are needed to convert an analog value to a digital number. • ATDCTL4 selects the sample period and PRS-Clock prescaler • SMP1,SMP0—sample time select bits. • Select the length of the second phase of the sample time in units of ATD conversion clock periods (Table 11.5)

  22. ATD Clock Frequency • Let m be the 5-bit number formed by PRS4-0. • Let fe be the frequency of the E clock. • The ATD clock frequency is fe/2(m+1). • The default value of m is 5 so the default ATD clock frequency is fe/12.

  23. ATD Clock (cont.) • Freescale recommends a clock rate from 500 kHz to 2Mhz. • Other issues: • For analog signals with white noise, we can add a low pass filter by increasing the ADC sample time, s. • For faster conversions, increase the clock frequency. • For signals with high slopes, dv/dt, a higher conversion time is needed. • Let n be the number of bits, then the time for one conversion is 2(m + 1)(s + n)/fe.

  24. Observation • The ADC frequency does not determine the data acquisition sampling rate, rather it determines how fast one ADC conversion occurs. • The sampling rate is determined by how often the software starts the ADC conversion.

  25. The ATDCTL5 Register • Writing to the ATDCTL5 register will start an ADC conversion. • Continuous conversions—SCAN =1. • Only one sequence occurs—SCAN =0. • CC,CB,CA select the analog input channel • The result registers are 16 bits. • The result is right justified when DJM = 1 and left justified if DJM =0. • When DSGN=1 the result will have a signed format; when DSGN=0 the result will be unsigned. • (See Table 11.6—formats for the 9S12 ADCs.)

  26. Example 11.2 • Design a device driver for the internal ADC. • Solution • ADC_in will be a function that performs one conversion. • ADC_init will initialize the ADC.

  27. Program 11.1 • Assembly and C are shown. • ADC_Init movb #$80, ATD0CTL2 ; power up • movb #$08, ATD0CTL3; 1 sample • movb #$05, ATD0CTL4; 10-bit • rts • Note in the above ADPU =1, S1C =1, and SRES8=0.

  28. Program 11.1 • Solution (cont.) • With m =5, and 24 Mhz E clock we have a 2 MHz ADCclock. • Assuming low noise, use the shortest possible sampling time (s = 4). • The conversion time is 7 microseconds.

  29. Program 11.1 • Note the lower portion of the program: • ADC_in staa ATD0CTL5 ; START AD, where REGA =$82. • Loop brclr ATD0STAT1, $01, Loop • ldd ATD0DR0 ; 10 bit result • rts • Note: for the 9S12C32 change all ATD0s to ATD.

  30. 11.5 Multiple Access Circular Queues • (MACQ)—used for performing digital signal processing on a data acquisition system. • It is fixed length and order preserving data structure (see Figure 11.12).

  31. MACQ • Useful for implementing digital filters and digital controllers (page 408) • d = (v[0] + 3v[1] – 3 v[2] –v[3])/6Δt • Where d is the derivative, v[i] are the most recent sample times and Δt is the sampling interval. • When a new sample is taken, v[1] = v[0], v[2] =v[1], v[3] =v[2] and the new sample becomes the next v[0].

  32. 11.6 Real-Time Data Acquisition • We need to sample at a fixed rate. • Perfect world—(ti – ti-1) = 1/fs where fs is the sampling frequency as required by the Nyquist theorem. • Imperfect world • Time jitter (δt)—maximum variation in the sample-to-sample time. • 1/fs – δt <(ti –ti-1) < 1/fs + δt

  33. 11.6 (cont.) • Section 9.2—9 cycles needed to process an interrupt (vector fetch, push registers). • These 9 cycles and the ISR are equal for every sample. • Problems • (1) instruction currently being executed at the time of the interrupt request—at most this is 13 cycles or 1.625 microseconds on an 8 Mhz 9S12--acceptible • (2) jitter could be much larger-- the main program could disable interrupts, which could cause jitter in the sampling—if interrupts need servicing they could also cause jitter.

  34. Example 11.3 • Design a real-time data acquisition system that samples a voltage signal, performs a digital differentiation and displays the slope on a LCD. The range of inputs is 0 to + 5 V with frequency components of 0 to 50 Hz.

  35. Example 11.3 • Solution: • Connect the input to PAD2 (any ADC input is ok.) • Sampling should be at 100 Hz or faster. • Output to LCD is about .4ms (see Program 8.7, 10 characters at 40 microseconds each. • Periodic output compare interrupt (Program 9.4) • Main program initializes: PLL, OC6, and AD or faster. • Output to LCD is about .4ms (see Program 8.7, 10 characters at 40 microseconds each. • Periodic output compare interrupt (Program 9.4) • Main program initializes: PLL, OC6, and ADC

  36. Example 11.3 (cont.) • See Figure 11.13—Flowchart • Main loop– wait for a sample, calculate the derivative, then output the slope. • Program 11.2—page 410-411

  37. Example 11.4 • Design an analog interface between a 30kΩ thermistor and the 9S12, so that temperatures between 20° and 45°C can be measured. • Solution– the thermistor is a transducer with its resistance proportional to temperature. • 30kΩ thermistor has resistance of 30kΩ at room temperature (25°C). • Figure 11.14 shows a circuit related to the thermistor.

  38. 11.7 Control Systems • A control system (Figure 11.15) is a collection of mechanical and electrical devices for “controlling” a physical plant, for example a DC motor. • The physical plant is described by “real state variables” and these variables are to be controlled. • A sensor and state estimator comprise a data acquisition system. • A closed loop control system uses the output of the state estimator in a feedback loop to drive the errors to zero. • The actuator is a transducer that converts the control system commands (U(t)) into driving forces (V(t)) that are applied to the physical plant.

  39. Example 11.5 • Design a control system that controls a DC motor in the range of 1000 to 2000 RPM • Solution: • One input will be the desired speed (RPM) stored as a decimal integer in a global variable called Desired. • The second input is the measured speed. • Figure 11.16 illustrates a flowchart showing the Error =Desired – Measured. • U is either increased or decreased (or remains the same at its max and min).

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