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//HDL Example 3-3 //---------------------- //Stimulus for simple circuit module stimcrct;

//HDL Example 3-3 //---------------------- //Stimulus for simple circuit module stimcrct; reg A,B,C; wire x,y; circuit_with_delay swd(A,B,C,x,y); initial begin A = 1'b0; B = 1'b0; C = 1'b0; #100 A = 1'b1; B = 1'b1; C = 1'b1; #100 $finish; end

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//HDL Example 3-3 //---------------------- //Stimulus for simple circuit module stimcrct;

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  1. //HDL Example 3-3 • //---------------------- • //Stimulus for simple circuit • module stimcrct; • reg A,B,C; • wire x,y; • circuit_with_delay swd(A,B,C,x,y); • initial • begin • A = 1'b0; B = 1'b0; C = 1'b0; • #100 • A = 1'b1; B = 1'b1; C = 1'b1; • #100 $finish; • end • endmodule • //Description of circuit with delay • module circuit_with_delay (A,B,C,x,y); • input A,B,C; • output x,y; • wire e; • and #(30) g1(e,A,B); • or #(20) g3(x,e,y); • not #(10) g2(y,C); • endmodule

  2. //HDL Example 4-10 • //------------------------------------------ • //Gate-level description of circuit of Fig. 4-2 • module analysis (A,B,C,F1,F2); • input A,B,C; • output F1,F2; • wire T1,T2,T3,F2not,E1,E2,E3; • or g1 (T1,A,B,C); • and g2 (T2,A,B,C); • and g3 (E1,A,B); • and g4 (E2,A,C); • and g5 (E3,B,C); • or g6 (F2,E1,E2,E3); • not g7 (F2not,F2); • and g8 (T3,T1,F2not); • or g9 (F1,T2,T3); • endmodule • //Stimulus to analyze the circuit • module test_circuit; • reg [2:0]D; • wire F1,F2; • analysis fig42(D[2],D[1],D[0],F1,F2); • initial • begin • D = 3'b000; • repeat(7) • #10 D = D + 1'b1; • end • initial • $monitor ("ABC = %b F1 = %b F2 =%b ",D, F1, F2); • endmodule

  3. //Solution to supplement Experiment 7(a) • //BEHAVIORAL DESCRIPTION OF 7483 4-BIT ADDER. • module _7483(Sum,A,B,Cin,Cout); • input [3:0] A,B; • input Cin; • output [3:0] Sum; • output Cout; • reg [3:0] Sum; • reg Cout; • always @(A or B or Cin) • {Cout,Sum} = A + B + Cin; • endmodule

  4. //Solution to supplement Experiment 8(a) • //Behavioral description of 7474 D flip-flop • module _7474 (Q,D,CLK,preset,clear); • output Q; • input D,CLK,preset,clear; • reg Q; • always @ (posedge CLK or negedge preset or negedge clear) • if (~preset) Q = 1'b1; • else if (~clear) Q = 1'b0; • else Q = D; • endmodule

  5. //Solution to supplement Experiment 10 • //Behavioral description of 74161 • //P and T are treated as a single enable input "Count". • module _74161(Data_in,Q,Co, Load, Count, CLK, Clr); • input Load, Count, CLK, Clr; • input [3:0] Data_in; • output [3:0] Q; • output Co; • reg [3:0] Q; • wire Co; • //Co=1 when Q is all 1's AND count is enabled. • assign Co = (&Q) & Count; • always @(negedge Clr or posedge CLK) • if (~Clr) Q = 0; • else if (~Load) Q = Data_in; • else if (Count) Q = Q + 4'b1; • else Q = Q; • endmodule

  6. //Solution to supplement Experiment 11(b) • //Behavioral description of 74157 MUX (Fig. 11-17). • module _74157(Y,A,B,Sel,Str); • input [1:4] A,B; • input Sel,Str; • output [1:4] Y; • reg [1:4] Y; • always @(A or B or Sel or Str) • if (Str==1) Y = 4'b0; • else if (Sel==0) Y = A; • else Y = B; • endmodule

  7. //Solution to supplement experiment 13(a) • //HDL description of 74189 16x4 RAM. • module _74189 (DataIn, DataOut, Addr, CS, WE); • input [3:0] DataIn, Addr; • input CS, WE; // CS and WE active-low. • output [3:0] DataOut; //Hi-Z during write or if memory disabled. • tri [3:0] DataOut; //Three-state output. • reg [3:0] Ram [0:15]; //16 x 4 memeory. • assign DataOut = (~CS && WE) ? ~Ram[Addr] : 4'bz; • always @(CS or WE or DataIn or Addr) • if (~CS && ~WE) Ram[Addr] = DataIn; • endmodule

  8. //Solution to supplement Experiment 14 • //DESCRIPTION Of 74194 SHIFT-REGISTER (Fig. 11-19) • module _74194(Q, DataIn, SIR, SIL, S1, S0, Clk, Clr); • input SIR, SIL, S1, S0, Clk, Clr; //Clr is async active-low. • input [1:4] DataIn;// 1,2,3,4 => A,B,C,D in Fig.11-19 • output [1:4] Q; • reg [1:4] Q; • wire S1, S0; • parameter NoChange = 2'b00, Shr = 2'b01, Shl = 2'b10, Ld = 2'b11; • always @(posedge Clk or negedge Clr) • if (~Clr) Q = 0; • else • case ({S1,S0}) • NoChange: Q = Q; • Shr: Q = {SIR,Q[1:3]}; • Shl: Q = {Q[2:4],SIL}; • Ld: Q = DataIn; • endcase • endmodule

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