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Design and Implementation of VLSI Systems (EN0160) Lecture 24: Sequential Circuit Design (2/3)

Design and Implementation of VLSI Systems (EN0160) Lecture 24: Sequential Circuit Design (2/3). Prof. Sherief Reda Division of Engineering, Brown University Spring 2007. [sources: Weste/Addison Wesley – Rabaey/Pearson]. A Flip-flop is a pair of back-to-back latches.

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Design and Implementation of VLSI Systems (EN0160) Lecture 24: Sequential Circuit Design (2/3)

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  1. Design and Implementation of VLSI Systems (EN0160) Lecture 24: Sequential Circuit Design (2/3) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

  2. A Flip-flop is a pair of back-to-back latches

  3. Sequencing timing terminology

  4. Max-Delay (setup) constraint: Flip-flops

  5. Max-Delay (setup) constraint: 2-phase latches

  6. Max-Delay (setup) constraint: Pulsed latches

  7. Example Determine the maximum logic propagation delay available within a 500ps clock cycle Using Flip-flops: tpd=500-(65+50) = 385ps Using Two-phase transparent latches: tpd=500-2*40 = 420ps Pulsed latches with 80ps pulse width: tpd=500-40 = 460ps

  8. Min-delay (hold) constraint: Flip-flip

  9. Min-delay (hold) constraint: 2-phase latches

  10. Min-delay (hold) constraint: Pulsed latch

  11. Example Determine the minimum logic contamination delay in each clock cycle (or half-cycle, for two-phase latches) Using Flip-flops: tcd=30-35 = 0ps tcd=30-35=0ps Using Two-phase transparent latches (duty 50%): tcd=30-35-60=0ps Using Two-phase transparent latches (60ps nonoverlap): Pulsed latches with 80ps pulse width: tcd=30-35+80=75ps

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