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Progetto di circuiti su FPGA

Progetto di circuiti su FPGA. Flusso di Sviluppo. Descrizione comportamentale Simulazione comportamentale Sintesi Descrizione strutturale (Netlist) Simulazione con ritardi approssimativi Implementazione Simulazione dettagliata Download Simulazione sul campo. Descrizione Comportamentale.

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Progetto di circuiti su FPGA

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  1. Progetto di circuiti su FPGA

  2. Flusso di Sviluppo • Descrizione comportamentale • Simulazione comportamentale • Sintesi • Descrizione strutturale (Netlist) • Simulazione con ritardi approssimativi • Implementazione • Simulazione dettagliata • Download • Simulazione sul campo

  3. Descrizione Comportamentale • Descrizione del tutto ideale del funzionamento del dispositivo ad alto livello di astrazione • non prevede ritardi di alcun tipo Es: C <= (A + B)* C

  4. Sintesi • Traduzione dalla descrizione comportamentale all strutturale, ossia a livello di porte logiche (Netlist) • Si basa sulla presenza di opportune librerie • E’ suddivisa nelle seguenti fasi • Analisi(analisi sintattica del sorgente) • Compilazione • traduzione a livello RTL (Register Transfer Level) • estrazione delle macro • Ottimizzazione(miglioramento della logica, espansione delle macro) • E’ un procedimento “guidato” • abbisogna di opportuni vincoli Lib. Vincoli

  5. Descrizione Strutturale A B Z C D • Descrizione del circuito il termini di blocchi logici (porte, flip-flop, registri, memorie, …) presenti in libreria opportunamente collegatiossia in termini di NETLIST • Le informazioni portate da questa descrizione sono: • Ritardi della logica (ma non dei collegamenti) • Area occupata dalla logica (ma non dai collegamenti)

  6. Implementazione • Traduce la descrizione a celle logiche in una opportuna descrizione fisica • maschere per il layout (ASIC) • file di download (FPGA - CPLD) • Si divide in quattro fasi • Translate ( fusione con blocchi pre-configurati) • Mapping (mappatura della logica nei CLB)solo per FPGA • Placement(Posizionamento dei blocchi logici) • RoutingCollegamento tra CLB • Il procedimento si basa su vincoliimplementativi

  7. Descrizione Dettagliata • La descrizione del circuito e’ molto vicina a quelle che saranno le reali prestazioni. Vi sono infatti informazioni su • Ritardi della logica • Ritardi nei collegamenti • Area occupata dalla logica • Area occupata dai canali di collegamento • Dettaglio sull’ ubicazione di ogni singola porta logica e/o dei piedini di I/O

  8. Back Annotation • Alcuni dei risultati ottenuti ai vari passi del procedimento spesso vengono utilizzati in un procedimento di “back-annotation” ossia vengono riportati ai passi superiori quali vincoli o per avere descrizioni piu’ dettagliate del funzionamento del circuito anche ad alti livelli di astrazione • Vincoli • Ritardi

  9. ISE Software Flow FPGA Design Workshop

  10. Software makes a difference • Device capabilities are worthless if you can’t usethem in YOUR course • Design software should support all ranges of designsfrom CPLD to the high-density FPGA • Works with YOUR design flow • minimize impacts to the design cycle • work with the tools you already own

  11. Foundation Series ISE • Foundation Series ISE (Integrated Software Environment) • For PC platforms: Win98, Win2000, and NT4.0 • For UNIX platforms: HP and Solaris

  12. Xilinx Design Flow Plan & Budget Create Code/ Schematic HDL RTL Simulation Implement Functional Simulation Synthesize to create netlist Translate Map Place & Route Attain Timing Closure Timing Simulation Create Bit File

  13. Advanced design managementthrough project navigator • Unix & PC platforms • Complete file management • Automates design flow • Entry • Synthesis • Implementation • Simulation • Programming

  14. Device Support • New leading-edge device families • ISE advantages can be leveraged across all device families and design sizes

  15. Processes and Tools • Some tools are listed multiple times with different task names Step 1:Design Step 2: Synthesize to create netlist Step 3: Implement design Step 4: Configuration

  16. Context Sensitive Flow • Only relevant processes are displayed to the user • Guides the user to the “next step” for that source HDL Module Selected Process Available Includes Synthesis and P&R Only HDL Simulation process is available HDL Test Bench Selected

  17. ISE Push Button Flow • Select a desired end result -- all necessary processe and dependencies automatically run to produce the result • Simple three-step process to get results 2 1 3 Double Click Desired End Point Add Files Select Top Level

  18. Lab 1: ISE Flows Introduction to the ISE flow Step through the FPGA design flow with a simple design Download the generated bitstream to the XESS - XSA50 demo board

  19. Design Entry • Two design entry methods: HDL or schematic • Architecture Wizard and Core Generator available to assist design entry • Whichever method you use, you will need a tool to generate an EDIF netlist to program a Xilinx FPGA • Popular synthesis tools: Synplify, Leonardo Spectrum, FPGA Compiler II, and XST • Simulate design so that it works as expected! Plan & Budget Create Code/ Schematic HDL RTL Simulation . . . Functional Simulation Synthesize to create netlist

  20. Schematic Source File • Create a new schematic source: Project  New Source  Schematic • Components from Xilinx Unified Libraries • HDL keywords cannot be used on schematics • Unified components require all input pins to be connected • Tie unused pins, both inputs and outputs, to GND or VCC

  21. Options and Symbols • Components are divided into categories • Exact symbols are located in the Symbol box • Symbol Name Filter for easier search • Orientation • Rotate 0, 90,180, 270 • Mirror and rotate 0, 90, 180, 270 • The Options tab selections change, depending on which function is selected • For example, if you are adding a net name, the net name options would be shown

  22. HDL Source File • Types of HDL source files • VHDL logic description (.vhd extension) • Verilog logic description (.v extension) • ABEL-HDL logic description (.abl extension) • Selecting these source types will open a text editor for you to enter the design code

  23. Xilinx CORE Generator System GUI Cores can be organized by function, vendor, or device family Core type, version, device support, and vendor

  24. Core Customize Window Core Overview tab provides version information and a brief functional description Contact tab provides information about the vendor Parameters tab allows you to customize the core Data sheet access

  25. What is Implementation? • More than just “Place & Route” • Implementation includes many phases • Translate: Merge multiple design files into a single netlist • Map: Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs) • Place & Route: Place components onto the chip, connect them, and extract timing data into reports • Each phase generates files that allow you to use other Xilinx tools (such as Floorplanner, FPGA Editor, XPower, Multi-Pass Place & Route)

  26. Implement • Each implementation stage can be expanded to view the available sub-tools and sub-processes • Translate • Create post-translate simulation model • Map • Floorplan • Manual route with FPGA Editor • Place & Route • Static timing • Floorplanner, view placed design • FPGA Editor, view routed design • Analyze power

  27. Download • Once a design is implemented, you must create a file that the FPGA can understand • This file is called a bit stream: a BIT file (.bit extension) • The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information

  28. Program the FPGA • There are two ways to program an FPGA • Through a PROM device • You will need to generate a file that the PROM programmer will understand • Directly from the computer • Use the iMPACT configuration tool

  29. RTL Viewer for XST • Helps debug design connectivity, design speed

  30. Architecture Wizards • Simplifies design of complex components • Generates HDL files & .ucf • Supports: • DCM • RocketIOTM transceivers • Including Channel Bonding

  31. State Diagram Source Files with .dia extension Selecting this source type will invoke StateCAD

  32. HDL Bencher 2) Choose Clocks 3) Associate Signals with Clocks or Assign as Asynchronous • Multiple Clock and Asynchronous Signal Support 1) Select Multiple Clocks and/or Asynch Signal Support

  33. HDL Bencher 4) Specify Timing for Each Clock 5) Define Waveforms • Multiple Clock and Asynchronous Signal Support

  34. Incremental DesignMake small changes quickly! • Re-implements only the changed modules • Keeps placement and routing • Easy set-up through floorplanningalong HDL hierarchy boundaries • Works with HDL designs • don’t optimize across hierarchy • More turns per day • More repeatable results

  35. PACEsimplifies pin and area assignments • PACE (Pinout and Area Constraints Editor) • Create groups for busses andstandard outputs • Color-coded banks • Drag-and-drop pin assignments • Interactive DRC • Automatic differential I/O pairing • Logic size to area checking

  36. Constraints Improvement Wizard • Gives suggestions on how to constrain unconstrained paths

  37. Summary • The Xilinx design process contains only four steps: design, synthesize, implement, configure • The Xilinx design process can all be done through the ISE Project Navigator

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