Are classical design flows suitable below 0.18 m ? ISPD 2001

1. Are classical design flows suitable below 0.18m?ISPD 2001 Wolfgang Roethig Senior Engineering Manager EDA R&D Group NEC Electronics Inc. WR0999.ppt-1

2. Classical Design Approaches • Low-end ASIC • automated design process, huge margin to guarantee functionality • fast TAT, yet sub-optimal use of process technology Full-custom design • hand-craft the design, transistor-level analysis • time-consuming methodology, usable only for standard products • High-end ASIC design must bridge the gap • fast TAT through automation, yet more sophisticated tools • aggressive design, but still sign-off guarantee

3. How to partition a complex SOC design into manageable blocks? How to check the entire design for localized voltage drops? How to analyze and reduce chip power consumption? How to calculate and fix timing in the presence of crosstalk and noise? How to ensure reliability against electromigration and hot electron effects? How to guarantee manufacturability by correct layout? New ASIC design issues A VDSM design flow must solve all these issues

4. D delay % @ wire length (3rd metal in 0.18u) victim 2x strength 8x strength routing pitch aggressor + 70 % @ 0.5 mm + 10 % @ 1 mm 2x strength single + 100 % @ 1 mm + 60 % @ 3 mm + 20 % @ 0.5 mm + 0 % @ 1 mm double + 40 % @ 1 mm + 10 % @ 3 mm 8x strength + 30 % @ 0.5 mm + 10 % @ 1 mm double + 40 % @ 1 mm + 30 % @ 3 mm + 70 % @ 0.5 mm + 40 % @ 1 mm single + 100 % @ 1 mm + 90 % @ 3 mm Example: crosstalk Two signals on adjacent wires switch simultaneously Delay increases up to 100% with single pitch 2x drive aggressor affects even 8x drive victim Delay increases up to 40% even with double pitch Significant effect even for 0.5 mm wire

5. 0.35m 0.25m 0.18m Technology Power / Power(0.35m) Current / Current (0.35m) 0.07 mW 0.04 mW 0.02 mW supply voltage max. clock frequency max. # gates power / gate / MHz 3.3 V 6 Meg 1 120 MHz 1 2.9 2.5 V 2.2 230 MHz 12 Meg 34 Meg 1.8 V 11.3 6.12 450 MHz Example: power and current density • Power consumption in 0.18m 6 times higher than in 0.35m • Current density in 0.18m 10 times higher than in 0.35m • Therefore dramatic increase in electromigration and voltage drop effects max. numbers are absolute technology limits power = # gates x frequency x power / gate / MHz current = power / supply voltage

6. Global antenna rules Electromigration &hot electron checkfor cells Electromigration &hot electron checkfor cells, avg. current limit Layer-specific antenna rules Electromigration &hot electron check forcells and interconnect, avg. and peak current limit Layer-specific antenna rules and metal density rules Reliability and Manufacturability Technology Reliability Manufacturability • More complicated rules for design tools 0.35m No design issue No design issue 0.25m 0.18m 0.13m

7. Consequences • Signal integrity effects can not be handled in isolation • crosstalk is the effect of multiple interacting signals • voltage drop is a system-level effect • reliability and manufacturability rules reduce the degrees of freedom for timing optimization • timing affects xtalk and vice versa • timing affects power and vice versa • Design tools need to be signal-integrity literate • coherent and concurrent design and analysis of all signal integrity effects is required • transistor-level analysis is not feasible • need higher level abstract analysis models

8. 1998 0.25m 2000 0.18m 2002 0.13m RTL RTL RTL Synthesis Power consumption, Voltage drop RTL Planning Synthesis Gate Physical Synthesis Timing, Power, Signal Integrity Optimization Gate Gate-level planning Placement Physical Synthesis Timing Optimization Routing Timing, xtalk, antenna, electromigraqtion Routing Signal Integrity Correctness Timing check Routing Signal Integrity Check&Repair 2MG 100MHz 10MG 200MHz 30MG 400MHz Changing Design Environment

9. Need for advanced library modeling • Design flow will need common or compatible analysis backplane • Technology library and its components (cells, blocks, wires) need to be characterized • timing and power are not sufficient • crosstalk delay and noise, electromigration, hot electron effect, manufacturability must be described • Models must be • accurate for high performance ICs • efficient for analysis and optimization • suitable for designers (model specification) as well as for characterization, design and analysis tools (model usage) • The Advanced Library Format (ALF) provides a solution • Already proliferating in the industry • Emerging IEEE standard (see www.eda.org)

10. Conclusion • Classical ASIC design flow is changing • increasing complexity: hierarchical design • decreasing geometry: signal integrity • VDSM technology requires more aggressive design • not enough room for guard bands: physics are too severe • not enough time for manual work: designs are too large • New generation of design tools and flows • concurrent design and analysis for timing, power, signal integrity, manufacturability using advanced library models • Merge of design flows • SOC contains ASIC-style blocks and custom blocks • Hierarchical design, analysis and optimization enabled by abstract models of the blocks