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GND

Signal distribution on the JTAG cable. GND. HALT. TDI_1. TCK. TMS. VREF. TDO_10. We will try the buffer solution first, and if it doesn’t work, try one cut cable. GND. HALT. VREF. VREF. TDI_1. VREF. GND. TCK. TMS. Cut here. VREF. TDO_10. SN74LVC126A.

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GND

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  1. Signal distribution on the JTAG cable GND HALT TDI_1 TCK TMS VREF TDO_10

  2. We will try the buffer solution first, and if it doesn’t work, try one cut cable. GND HALT VREF VREF TDI_1 VREF GND TCK TMS Cut here VREF TDO_10 SN74LVC126A Using driver for TCK and TMS Results (2 iterations): all 10 boards are found. Successful configuration of boards 1, 4, 5, 6, 8, 9 Failure to configure boards 2, 3, 10 Using Xilinx USB programmer

  3. 3 shorter JTAG cable solution with drops of 3, 3, 4 each fed with a Xilinx programmer. All 3 cables the same. Cut here Using a shorter JTAG daisy chain cable (4 boards) JTAG recommended termination in place. All boards configure all times for 4 boards All boards configure all times for 3 boards (end board bypassed with switch) Using Xilinx USB programmer Place patch here

  4. 2 shorter JTAG cable solution with drops of 5 boards each fed with a Xilinx programmer. Cut here Using a shorter JTAG daisy chain cable (5 boards and no termination) 3 tries – all configure all times Using Xilinx USB programmer NOTE: initial try in this configuration did not work well as the cable used was damaged (by cutting the traces to be used for the driver test) and the traces could not be reliably repaired. This cable did not work with termination attached. Place patch here

  5. Conclusions • The five drop daisy chain works reliably. • We have fabricated three 5-drop daisy chain cables from the rest of the flex cables fabricated for the run. • The operating configuration will consist of two 5-drop JTAG daisy chain cables driven with Xilinx USB JTAG programmers. • We will bring the Digilent JTAG programmers (10) and the adapter boards as a backup.

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