Interface Design Compute Memory Timing

1. Interface DesignComputeMemory Timing Omid Fatemi (omid@fatemi.net)

2. Outline • Connecting to micro-processor • Timing of microprocessor • Timing of memory • Interfacing memory

3. Compute Convey Cooperate Typical Interface Design Connect Sense Reality Touch Reality Connect Transform Embedded Systems Micros Assembler, C Real-Time Memory Peripherals Timers DMA Busses Protocols Standards PCI IEEE488 SCSI USB & FireWire CAN PC interfaces HCI

4. Processor Timing Diagramfor any memory read machine cycle

5. Processor Timing Diagramfor any memory write machine cycle

6. When interfacing memory chips to a microprocessor, consider the following: • TAVDV – address access time • TRLDV – read access time • TDVWH – memory setup time • TWHDX – data hold time • TWLWH – write pulse width Refer to 8088 data manual

7. Address Access Time (TAVDV)

8. Timing Requirements during Memory Read • TAVDV • 3TCLCL – TCLAV – TDVCL • Address Access Time • from Address is Valid to Data is Valid

9. Read Access Time (TRLDV)

10. Timing Requirements during Memory Read • TRLDV • 2TCLCL – TCLRL – TDVCL • Read Access Time • from Read Signal is Low to Data is Valid

11. Memory Setup Time (TDVWH)

12. Timing Requirements during Memory Write • TDVWH • 2TCLCL – TCLDV +TCVCTX • Memory Setup Time • from Data is Valid to Write Signal is High

13. Data Hold Time (TWHDX)

14. Timing Requirements during Memory Write • TWHDX • TCLCH – X • Data Hold Time (after WR’) • from Write Signal is High to Data is Invalid (Inactive)

15. Write Pulse Width / Write-Time (TWLWH)

16. Timing Requirements during Memory Write • TWLWH • 2TCLCL – Y • Write Pulse Width / Write-Time • from Write Signal is Low to Write Signal is High

17. 8088 MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS

18. Computation of Timing Requirements for 8088 using a 4Mhz Clock • TAVDV • 3TCLCL – TCLAVmax – TDVCLmin • 3(250 ns) – 110 ns – 30 ns • 610 ns • TRLDV • 2TCLCL – TCLRLmax – TDVCLmin • 3(250 ns) – 165 ns – 30 ns • 555 ns

19. 8088 MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS

20. Computation of Timing Requirements for 8088 using a 4Mhz Clock • TDVWH • 2TCLCL – TCLDVmax +TCVCTXmin • 2(250 ns) – 110 ns + 10 ns • 400 ns • TWHDX • TCLCH – X • 118 ns – 30 ns • 88 ns • TWLWH • 2TCLCL – Y • 2(250 ns) – 60 ns • 440 ns

21. Timing Requirements for 8088 using a 4Mhz Clock • TAVDV = 610 ns • TRLDV = 555 ns • TDVWH = 400 ns • TWHDX = 88 ns • TWLWH = 440 ns

22. Can we interface a 6264 to the 8088 chip which uses a 4MHz clock?

23. Timing Requirements for 6264 SRAM • TAVDV = ? • TRLDV = ? • TDVWH = ? • TWHDX = ? • TWLWH = ?

24. HM6264B - 8L HM6264B - 10L Symbol Parameter Units Min Max Min Max t Read cycle time 85 100 ns RC t Address access time 85 100 ns AA t Chip select access time (CS1’) 85 100 ns CO1 t Chip select access time (CS2’) 85 100 ns CO2 t Output enable to output valid 45 50 ns OE Chip selection to output in low - Z t 10 10 ns LZ1 (CS1) Chip selection to output in low - Z t 10 10 ns LZ2 (CS2) t Output enable to output in low - Z 5 5 ns OLZ Chip deselection in to output i n t 0 30 0 35 ns HZ1 high - Z (CS1’) t HM6264B Series Read TIMING REQUIREMENTS Chip deselection in to output in 0 30 0 35 ns HZ2 high - Z (CS2’) t Output disable to output in high - Z 0 30 0 35 ns OHZ t Output hold from address change 10 10 ns OH

25. HM6264B Series Write TIMING REQUIREMENTS

26. HM6264B Series Read Timing Diagram

27. HM6264B Series Write Timing Diagram

28. Timing Requirements for 6264 SRAM • TAVDV = tAA • TRLDV = tOE • TDVWH = tDW • TWHDX = tDH • TWLWH = tWP

29. Timing Requirements for HM6264B-8L • TAVDV = tAA = ? • TRLDV = tOE = ? • TDVWH = tDW = ? • TWHDX = tDH = ? • TWLWH = tWP = ?

30. HM6264B Series Read TIMING REQUIREMENTS

31. HM6264B Series Write TIMING REQUIREMENTS

32. Timing Requirements for HM6264B-8L • TAVDV = tAA = 85 ns • TRLDV = tOE = 45 ns • TDVWH = tDW = 40 ns • TWHDX = tDH = 0 ns • TWLWH = tWP = 55 ns

33. Comparing Timing Requirements of 8088 (using 4 Mhz clock) and HM6264B-8L

34. Can we interface a 2764 to the 8088 chip which uses a 4MHz clock?

35. Timing Requirements for 2764 EPROM • TAVDV = ? • TRLDV = ? • TDVWH = ? • TWHDX = ? • TWLWH = ?

36. M2764A Read Mode AC Characteristics

37. M2764A Read Mode Timing Diagram

38. Timing Requirements for 2764 EPROM • TAVDV = tAVQV • TRLDV = tGLQV • TDVWH = N/A • TWHDX = N/A • TWLWH = N/A

39. Timing Requirements for 2764 EPROM • TAVDV = tAVQV = ? • TRLDV = tGLQV = ? • TDVWH = N/A • TWHDX = N/A • TWLWH = N/A

40. M2764A Read Mode AC Characteristics

41. Timing Requirements for M2764A-3 • TAVDV = tAVQV = 180 ns • TRLDV = tGLQV = 65 ns • TDVWH = N/A • TWHDX = N/A • TWLWH = N/A

42. Comparing Timing Requirements of 8088 (using 4 Mhz clock) and M2764A-3

43. What if we need to interface a “slow” memory to the 8088?

44. Comparing Timing Requirements of 8088 (using 4 Mhz clock) and a certain “slow” memory chip

46. Recall:Write Pulse Width / Write-Time (TWLWH)

47. Write Pulse Width / Write-Time (TWLWH) w/ 1 wait state

48. Comparing Timing Requirements of 8088 (using 4 Mhz clock) and a certain memory chip caused by 1 wait state during a memory write on the “slow” memory chip

49. How do we produce a wait state? • By turning the READY input of the 8088 microprocessor to LOW