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Viterbi Decoder: Presentation #1

Overall Project Objective: Design of a high speed Viterbi Decoder. Stage 1: 21 Jan. 2004 Project Proposal. Viterbi Decoder: Presentation #1. M1. Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun. Status. Design Proposal (done) Architecture (in progress) To be done: Floor Plan

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Viterbi Decoder: Presentation #1

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  1. Overall Project Objective: Design of a high speed Viterbi Decoder Stage 1: 21 Jan. 2004 Project Proposal Viterbi Decoder: Presentation #1 M1 Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun

  2. Status • Design Proposal (done) • Architecture (in progress) • To be done: • Floor Plan • Gate Level Design • Component Layout • Chip Layout • Spice Simulation of Entire Chip

  3. What isViterbi Decoder? • A processor that implements the Viterbi algorithm • Widely used in digital communication and storage • Cellular telephone: convolutional code decoding • Magnetic, optical disk drives: channel detector

  4. WhyViterbi Decoder • Example : Hard disk drive: GOOD 01000111, 01001111, 01001111, 01000100 01010011, 01001100, 01001111, 01010111 SLOW • Viterbi algorithm: Take the received signal Find out the most likely input sequence

  5. The Viterbi Algorithm • Calculation along the trellis • Implementation Architecture Branch Calculation Unit Add Compare Select Unit Maximum Likelihood Path Search Trace FIFO Trace Back Control Unit

  6. Schematic Diagram C0 C1 C2 C3 Cn-1 Cn Input … BCU Control Logic Input_valid … FIFO & trace back ACS D D … D … D D … D ……….. ……….. Vdd D D D D Gnd Clock ML Search Reset Output_valid Output

  7. Transistor Estimate 1000 Design Goal: High speed Above: No. of components x No. of transistors

  8. Other Ideas • Equalizer • Fast Fourier Transform • Adaptive Filter • Auto-Regressive Filter

  9. Questions?

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