Nick McKeown

1. Spring 2012 Lecture 2,3 Output Queueing EE384x Packet Switch Architectures Nick McKeown

2. Outline • Output Queued Switches • Rate and Delay guarantees

3. Link 1, ingress Link 1, egress Link 2, ingress Link 2, egress Link 3, ingress Link 3, egress Link 4, ingress Link 4, egress Output queued switch Link rate, R Link rate, R Link 2 Link 1 Link 3 R R Link 4 R R R R

4. Characteristics Arriving packets immediately written to output queue. Isolation: Packets unaffected by packets to other outputs. Work conserving: an output line is always busy when there is a packet in the switch for it. Throughput: Maximized. Average delay: Minimized. We can control the rate of individual flows, and the delay of individual packets

5. The shared memory switch A single pool of memory Link 1, ingress Link 1, egress Link 2, ingress Link 2, egress R R Link 3, ingress Link 3, egress R R Link N, ingress Link N, egress R R

6. Questions • Is a shared memory switch work conserving? • How does average packet delay compare to an output queued switch? • Packet loss?

7. Memory bandwidth OQ switch Per output: (N+1)R Switch total: NR(N+1) @ N2R Shared Memory Switch: Switch total: 2NR

8. Capacity of shared memory switches Assume: 2ns random access SRAM 500MHz bus; separate read and write 64byte wide bus Smallest packet size = 64bytes 500MHz * 64bytes * 8~= 256Gb/s 2ns SRAM 1 Shared Memory 2 64 byte bus N

9. Outline • Output Queued Switches • Rate and Delay guarantees

10. Rate Guarantees Problem #1: In a FIFO queue, all packets and flows receive the same service rate. Solution: Place each flow in its own output queue; serve each queue at a different rate.

11. Fairness 10 Mb/s 0.55 Mb/s A 1.1 Mb/s 100 Mb/s C R1 e.g. an http flow with a given (IP SA, IP DA, TCP SP, TCP DP) 0.55 Mb/s B What is the “fair” allocation: (0.55Mb/s, 0.55Mb/s) or (0.1Mb/s, 1Mb/s)?

12. Fairness 10 Mb/s A 1.1 Mb/s R1 100 Mb/s D B 0.2 Mb/s What is the “fair” allocation? C

13. Max-Min FairnessA common way to allocate flows Nflows share a link of rate C. Flowfwishes to send at rate W(f), and is allocated rate R(f). • Pick the flow, f, with the smallest requested rate. • If W(f)< C/N, then set R(f) = W(f). • If W(f) > C/N, then set R(f) = C/N. • Set N = N – 1. C = C – R(f). • If N>0 goto 1.

14. Max-Min FairnessAn example Round 1: Set R(f1) = 0.1 Round 2: Set R(f2) = 0.9/3 = 0.3 Round 3: Set R(f4) = 0.6/2 = 0.3 Round 4: Set R(f3) = 0.3/1 = 0.3 W(f1) = 0.1 1 W(f2) = 0.5 C R1 W(f3) = 10 W(f4) = 5

15. Max-Min Fairness How can a router “allocate” different rates to different flows? First, let’s see how a router can allocate the “same” rate to different flows…

16. Fair Queueing • Packets belonging to a flow are placed in a FIFO. This is called “per-flow queueing”. • FIFOs are scheduled one bit at a time, in a round-robin fashion. • This is called Bit-by-Bit Fair Queueing. Flow 1 Bit-by-bit round robin Classification Scheduling Flow N

17. Weighted Bit-by-Bit Fair Queueing Likewise, flows can be allocated different rates by servicing a different number of bits for each flow during each round. R(f1) = 0.1 1 R(f2) = 0.3 C R1 R(f3) = 0.3 R(f4) = 0.3 Order of service for the four queues: … f1, f2, f2, f2, f3, f3, f3, f4, f4, f4, f1,… Also called “Generalized Processor Sharing (GPS)”

18. Packetized Weighted Fair Queueing (WFQ) Problem: We need to serve a whole packet at a time. Solution: • Determine what time a packet, p, would complete if we served flows bit-by-bit. Call this the packet’s finishing time, F. • Serve packets in the order of increasing finishing time. Theorem: Packet p will depart before F + TRANSPmax Also called “Packetized Generalized Processor Sharing (PGPS)”

19. Intuition behind Packetized WFQ • Consider packet p that arrives and immediately enters service under WFQ. • Potentially, there are packets Q = {q, r, …} that arrive after p that would have completed service before p under bit-by-bit WFQ. These packets are delayed by the duration of p’s service. • Because the amount of data in Q that could have departed before p must be less than or equal to the length of p, their ordering is simply changed. • Packets in Q are delayed by the maximum duration of p. (Detailed proof in Parekh and Gallager)

20. Calculating F • Assume that at time t there are N(t) active (non-empty) queues. • Let R(t) be the number of rounds in a round-robin service discipline of the active queues, in [0,t]. • A P bit long packet entering service at t0 will complete service in round R(t) = R(t0) + P.

21. Case 1: If packet arrives to non-empty queue, then Si = Fi-1 Case 2: If packet arrives at t0 to empty queue, then Si = R(t0) An example of calculating F Flow 1 R(t) Flow i Pick packet with smallest Fi & Send Calculate Si and Fi & Enqueue Flow N • In both cases, Fi = Si + Pi • R(t) is monotonically increasing with t, therefore • same departure order in R(t) as in t.

22. WFQ is complex • There may be hundreds to millions of flows; the linecard needs to manage a FIFO per flow. • The finishing time must be calculated for each arriving packet, • Packets must be sorted by their departure time. Naively, with m packets, the sorting time is O(logm). • In practice, this can be made to be O(logN), for N active flows: 1 Egress linecard 2 Calculate Fp Find Smallest Fp Departing packet Packets arriving to egress linecard 3 N

23. Delay Guarantees Problem #2: In a FIFO queue, the delay of a packet is determined by the number of packets ahead of it (from other flows). Solution: Control the departure time of each packet.

24. Simple deterministic model Cumulative number of bits that arrived up until time t. A(t) A(t) Cumulative number of bits D(t) Q(t) R Service Process, rate R time D(t) Properties ofA(t), D(t): A(t), D(t) are non-decreasing A(t) >= D(t) Cumulative number of departed bits up until time t.

25. Simple Deterministic Model Cumulative number of bits d(t) A(t) Q(t) D(t) time Queue occupancy: Q(t) = A(t) - D(t). Queueing delay, d(t), is the time spent in the queue by a bit that arrived at time t, (assuming that the queue is served FCFS/FIFO).

26. Deterministic analysis of a router queue FIFO delay, d(t) Cumulative bytes Model of router queue A(t) D(t) A(t) D(t) R Q(t) Q(t) m time

27. So how can we control the delay of packets? Assume continuous time, bit-by-bit flows for a moment… • Let’s say we know the arrival process, Af(t), of flow f to a router. • Let’s say we know the rate, R(f) that is allocated to flow f. • Then, in the usual way, we can determine the delay of packets in f, and the buffer occupancy.

28. Flow 1 R(f1), D1(t) A1(t) Classification WFQ Scheduler Flow N AN(t) R(fN), DN(t) Cumulative bytes Key idea: In general, we don’t know the arrival process. So let’s constrain it. A1(t) D1(t) R(f1) time

29. One way to bound the arrival process r Cumulative bytes Number of bytes that can arrive in any period of length t is bounded by: This is called “(s,r) regulation” A1(t) s time

30. dmax Bmax (s,r) Constrained Arrivals and Minimum Service Rate Cumulative bytes A1(t) D1(t) r s R(f1) time Theorem [Parekh,Gallager]: If flows are leaky-bucket constrained,and routers use WFQ, then end-to-end delay guarantees are possible.

31. The leaky bucket “(s,r)” regulator Tokens at rate,r Token bucket size,s Packets Packets One byte (or packet) per token Packet buffer

32. How the user/flow can conform to the (s,r) regulationLeaky bucket as a “shaper” Tokens at rate,r Token bucket sizes To network Variable bit-rate compression C r bytes bytes bytes time time time

33. Checking up on the user/flowLeaky bucket as a “policer” Router Tokens at rate,r Token bucket sizes From network C r bytes bytes time time

34. Policer Policer Classifier Classifier Policer Policer Packet switch with QoS Per-flow Queue Scheduler Per-flow Queue Per-flow Queue Scheduler Per-flow Queue • Questions: These results assume an OQ switch • Why? • What happens if it is not?

35. References • Abhay K. Parekh and R. Gallager“A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Single Node Case” IEEE Transactions on Networking, June 1993. • M. Shreedhar and G. Varghese“Efficient Fair Queueing using Deficit Round Robin”, ACM Sigcomm, 1995.