Sequential Circuits II: Edge Triggered Flip Flops

Sequential Circuits II:Edge Triggered Flip Flops

Quick Review:Latches and Flip-Flops • Latches: SR and D • Flip Flops • Master-Slave • Two stage • Output not changed until clock disabled • Edge triggered • Change happens when clock level changes

SR Latch

D Latch

Master Latch Slave Latch Master-Slave Flip-Flop • Either master or slave is enabled, not both • Pulse triggered.

D-Type Positive-Edge Triggered • An edge triggered FF ignores the pulse while it is at a constant level and triggers only during a transition of a clock signal. • +ve edge vs –ve edge

Standard Symbols for Storage Elements S S D D R R C C D with 0 Control SR D with 1 Control SR (a) Latches S S D D C C R R C C Triggered D Triggered D Triggered SR Triggered SR (b) Master-Slave Flip-Flops D D C C Triggered D Triggered D (c) Edge-Triggered Flip-Flops • Master-Slave:Postponed outputindicators • Edge-Triggered:Dynamicindicator

Direct Inputs • Set/Reset independent of clock • Direct set or preset • Direct reset or clear • Often used for power-up reset

Clock Gating • Can gate clocks (to keep any FF from changing states, for example) • Clock gating used to reduce power drain • However, can cause clock skew • Clock edges at different times on different FFs • Clock skew also caused by wire lengths over chip

Next • State Diagrams • Registers

Sequential Circuits II: Edge Triggered Flip Flops