Some ideas for a tracking and timestamp pixel detector suitable for CLIC

1. Some ideas for a tracking and timestamp pixel detector suitable for CLIC Rafa Ballabriga, Michael Campbell, Xavier Llopart, Sami Vähänen CERN ESE

2. Outline • Assumptions for CLIC • The effect of segmentation on performance (noise and jitter) • The Timepix architecture and how it could be improved • Low mass bump bonding

3. Assumptions for CLIC • ~312 bunches per train spaced by 0.5ns • 50Hz bunch rate • Pixel size <= 15 mm • Detector diameter 3cm • Detector length ~20cm • Physics hit occupancy ~20 hits/train • Background ~2M hits/train • Pixel occupancy on inner layer ~ 10-2?? • Total power budget ~ 100mW/cm2 • Power cycling allows at least x10 more during up time • Each pixel records bunch number (or a multiple thereof) for a given train • Full readout between trains

4. Geometry for readout chip bump-bonded to Si Sensor

5. Assumption for noise and jitter calculations • Constant power dissipation 1W/cm2 • 70% of the power dissipated in the input stage (differential) • Collection time must be faster than shaping time • Charge sharing not taken into account • The input transistor size is calculated for optimal ENC (Equivalent Noise Charge) for a given pixel size and shaping time • First order CR-RC shaper

6. System schematic CFB VOUT ts IPR CinMOS ID CDET

7. Noise equation Noise Equation: Calculated from EKV model W=OptimumW(Pixel Side)

8. Geometry for readout chip bump-bonded to Si Sensor (input capacitance) CDET =e/xD Cpadlin=1pF/cm Cpad=50fF (25mm diameter pad) eis the permittivity (1.054 10-12 F cm-1 for Si) and xD is the thickness of the depletion region (xD equals 100mm in the results presented in this report)

9. ENC as a function of shaping time ENC as a function of the pixel side for different shaping times. (1W/cm2, Si sensor Ileak = 1mA/cm2)

10. Timing • Triangular signal, Qin=7000e- Giovanni Anelli, FEE 2006 Perugia

11. Jitter

12. Timepix Pixel Schematic Previous Pixel Clk_Read Clk_Countb Mux 4 bits thr Adj Mask Mux Preamp Input Disc 14 bits Shift Register Shutter Timepix Synchronization Logic THR Shutter_int Ctest P0 Conf Testbit Polarity P1 8 bits configuration Test Input Ovf Control Clk_Count Clk_Read Next Pixel Analog Digital

13. Area use in Medipix3 pixel Area pixel: 55x55mm2 Preamplifier~1/8 pixel surface Analog part~30x30mm (if charge summing is not needed) (130nm IBM CMOS process) • Preamplifier • Shaper • Two discriminators with 4-bit threshold adjustment • Configuration bits • Arbitration logic for charge allocation • Control logic • Configurable counter.

14. CLICpix readout architecture • Pixels 15 mm x 15 mm • 65nm technology or less • Matrix 1024 x 1024 pixels • 1W/cm2 analog on power (100mW/cm2 DC) • Each pixel records bunch number (or multiple thereof) • Timing precision 10ns or better • ToT in each pixel • All data read out at end of train

15. Assembly Unique Control Smoltek’s technology enables control of the morphology and properties of carbon nanofibers Carbon Nanofiber* • Hybrid pixel with thinned readout chip (50mm thick) and thin sensor (100mm thick) • Carbon nanofibre bumps • Carbon nanofibre heat sink • Electromigration • occurs at >106A/cm2 • 100 % Yield • diameter of 20- • 200 nm • height from 50 nm- • 3 μm • Compatible with • CMOS-processes