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Simplified MIPS Lite Implementation Overview

A simplified overview of MIPS Lite implementation, covering instruction access, memory usage, and ALU operations. Learn about register file control and data access procedures. Timing assumptions and control codes are outlined for clarity.

williamholloway
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Simplified MIPS Lite Implementation Overview

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  1. PC Next PC Logic Address Instruction Memory Simplified Overview Instruction Access the Instruction from Memory

  2. PC Next PC Logic Address Instruction Memory Simplified Overview Instruction Register File Access the Data from Registers

  3. PC Next PC Logic Address Instruction Memory Simplified Overview Instruction Register File ALU Perform the Instruction

  4. PC Next PC Logic Address Instruction Memory Simplified Overview Instruction Addr Register File Data Memory ALU Data Out Data In Write the Result

  5. PC Next PC Logic Address Instruction Memory Simplified Overview Instruction Addr Register File Data Memory ALU Data Out Data In Timing Assumption

  6. MIPS - Lite Consider the following instructions for implementation INSTRUCTION OP FUNCT R type op rs, rt, rd add 0 32 subtract 0 34 AND 0 36 OR 0 37 set on less than 0 42 load word 35 na lw rt, imm(rs) store word 43 na sw rt, imm(rs) branch equal 4 na beq rs, rt,imm

  7. Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT R1 R2 Rw Registers R1 R2 Rw Dw Dr1 Dr2

  8. Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs R1 rt R2 rd Rw Registers R1 R2 Rw Dw Dr1 Dr2

  9. Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs R1 rt x R2 rd rt Rw Registers R1 R2 Rw Dw Dr1 Dr2

  10. Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs R1 rt x rt R2 rd rt x Rw Registers R1 R2 Rw Dw Dr1 Dr2

  11. Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw Registers R1 R2 Rw Dw Dr1 Dr2

  12. Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw Registers rs rt rd R1 R2 Rw Dw Dr1 Dr2 0 1 mux RegDst = Register Destination for the Write Register

  13. Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw 1 0 x x RegDst rs rt rd R1 R2 Rw Dw Dr1 Dr2 0 1 mux RegDst = Register Destination for the Write Register

  14. Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw 1 0 x x RegDst RegWrite = Write the selected register with Write Data Input rs rt rd R1 R2 Rw Dw Dr1 Dr2 0 1 mux RegDst = Register Destination for the Write Register

  15. Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw 1 0 x x RegDst 1 1 0 0 RegWrite = Write the selected register with Write Data Input rs rt rd R1 R2 Rw Dw Dr1 Dr2 0 1 mux RegDst = Register Destination for the Write Register

  16. PC Next PC Logic Address Instruction Memory Simplified Overview Instruction Addr Register File Data Memory ALU Data Out Data In

  17. ALU Operation Control Lines ALU Control Code Function Bnegate Operation 0 00 and 0 01 or 0 10 add 1 10 subtract 1 11 set on less than

  18. ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add 0 32 subtract 0 34 AND 0 36 OR 0 37 set on less than 0 42 load word 35 na store word 43 na branch equal 4 na

  19. ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add 0 32 10 subtract 0 34 10 AND 0 36 10 OR 0 37 10 set on less than 0 42 10 load word 35 na 00 store word 43 na 00 branch equal 4 na 01 ALUOp = 10 if the operation depends on the funct field 00 if add 01 if subtract

  20. ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add 0 32 10 add subtract 0 34 10 subtract AND 0 36 10 and OR 0 37 10 or set on less than 0 42 10 slt load word 35 na 00 add store word 43 na 00 add branch equal 4 na 01 subtract ALUOp = 10 if the operation depends on the funct field 00 if add 01 if subtract

  21. ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add 0 32 10 add 010 subtract 0 34 10 subtract 110 AND 0 36 10 and 000 OR 0 37 10 or 001 set on less than 0 42 10 slt 111 load word 35 na 00 add 010 store word 43 na 00 add 010 branch equal 4 na 01 subtract 110

  22. ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input a b Zero a b ALU Result ALU control funct ALUOp

  23. ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input a b Dr1 Dr2 Zero a b ALU Result ALU control funct ALUOp

  24. Load Word & Store Word ( I – type ) lw rt, imm16 (rs) or sw rt, imm16 ( rs) op rs rt imm16 lw # load word M[ R[rs] + sign_ext(imm16) ] R[rt] sw # store word R[rt] M[ R[rs] + sign_ext(imm16) ]

  25. ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input Dr1 ext(imm) a b Dr1 Dr2 Zero a b ALU Result ALU control funct ALUOp

  26. ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input Dr1 ext(imm) a b Dr1 Dr2 Dr1 Dr2 Zero a b ALU Result ALU control funct ALUOp

  27. ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input Dr1 ext(imm) a b Dr1 Dr2 Dr1 Dr2 Zero Dr1 a b ALU Result Dr2 0 1 sign ext 6 imm ALU control funct ALUSrc ALUOp

  28. ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input Dr1 ext(imm) a b Dr1 Dr2 Dr1 Dr2 ALUSrc = ALU second reg control Dr1 a b Zero ALU Result Dr2 0 1 sign ext 6 imm ALU control funct ALUSrc ALUOp

  29. ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Input Dr1 ext(imm) a b Dr1 Dr2 Dr1 Dr2 0 1 1 0 ALUSrc = ALU second reg control Dr1 a b Zero ALU Result Dr2 0 1 sign ext 6 imm ALU control funct ALUSrc ALUOp

  30. PC Next PC Logic Address Instruction Memory Simplified Overview Instruction Addr Register File Data Memory ALU Data Out Data In

  31. Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm MemWrite Result Addr Dr Dw Dr2 MemRead Data Memory

  32. Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw 1 0 x x RegDst 1 1 0 0 RegWrite = Write the selected register with Write Data Input rs rt rd R1 R2 Rw Dw Dr1 Dr2 0 1 mux RegDst = Register Destination for the Write Register

  33. Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control MemWrite MemRead MemWrite Addr Result Dr Dw Dr2 MemRead Data Memory

  34. Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control MemWrite MemRead 0 0 1 0 MemWrite Addr Result Dr Dw Dr2 MemRead Data Memory

  35. Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control MemWrite MemRead 0 0 1 0 0 1 0 0 MemWrite Addr Result Dr Dw Dr2 MemRead Data Memory

  36. Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control MemWrite MemRead MemtoReg 0 0 1 0 0 1 0 0 mux MemWrite 0 1 to Register File Dw Addr Result Dr Dw Dr2 MemtoReg Selects data memory or ALU output to Register Write Data MemRead Data Memory

  37. Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control MemWrite MemRead MemtoReg 0 0 1 0 0 1 0 0 0 1 x x mux MemWrite 0 1 to Register File Dw Addr Result Dr Dw Dr2 MemtoReg Selects data memory or ALU output to Register Write Data MemRead Data Memory

  38. PC Next PC Logic Address Instruction Memory Simplified Overview Instruction Addr Register File Data Memory ALU Data Out Data In

  39. add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm PC Arithmetic 4 ALU 0 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 ? imm16 sign ext 32 16

  40. add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm PC Arithmetic 4 ALU 0 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 imm16 sign ext Zero 32 16 Branch

  41. add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm PC Arithmetic add lw sw beq Control Branch 4 ALU 0 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 imm16 sign ext Zero 32 16 Branch

  42. add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm PC Arithmetic add lw sw beq Control 0 0 0 1 Branch 4 ALU 0 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 imm16 sign ext Zero 32 16 Branch

  43. Control Summary Inputs R type lw sw beq Op 000000 100011 101011 000100 Outputs RegDst 1 0 x x ALUSrc 0 1 1 0 MemtoReg 0 1 x x RegWrite 1 1 0 0 MemRead 0 1 0 0 MemWrite 0 0 1 0 Branch 0 0 0 1 ALUOp1 1 0 0 0 ALUOp2 0 0 0 1

  44. Review Fig 4.15 page 320 / Fig. 4.17 page 322 Review Timing

  45. Add Jump Instruction j Label go to Label op address 2 address 6 bits 26 bits The complete 32 bit address is : address 00 4 bits 26 bits 2 bits Upper 4 bits of the Program Counter, PC jump uses word addresses address * 4 = address:00 This is Pseudodirect Addressing. Note: 256 MB word boundaries

  46. Jump Instruction Data Path Jump 28 32 shift left 2 address Instruction[25-0] 1 0 : PC+4 (31-28) 4 4 “Other” Next Instr Logic Add PC

  47. Jump Instruction Data Path Jump = Opcode(2) Jump 28 32 shift left 2 address Instruction[25-0] 1 0 : PC+4 (31-28) 4 4 “Other” Next Instr Logic Add PC

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