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ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Low Voltage Low-Power Devices

ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Low Voltage Low-Power Devices. Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu

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ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Low Voltage Low-Power Devices

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  1. ELEC 5270/6270 Fall 2007Low-Power Design of Electronic CircuitsLow Voltage Low-Power Devices Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.html ELEC6270 Fall 07, Lecture 5

  2. Capacitances VDD Source C1 Drain In Out Drain C2 CW Source GND ELEC6270 Fall 07, Lecture 5

  3. Miller Capacitance VDD C1 In Out CM C2 CW GND ELEC6270 Fall 07, Lecture 5

  4. Before Transition VDD C1 +VDD 0 In = 0 Out = VDD CM C2 CW GND ELEC6270 Fall 07, Lecture 5

  5. After Transition VDD Energy from supply = 2 CM VDD2 Effective capacitance = 2 CM from pull-up devices of previous gate C1 +VDD 0 In Out CM C2 CW GND ELEC6270 Fall 07, Lecture 5

  6. Capacitances in MOSFET Cgs Cgd Gate Gate oxide Source Drain Cg Cd Cs Bulk ELEC6270 Fall 07, Lecture 5

  7. Bulk nMOSFET Polysilicon Gate Drain W Source n+ n+ L p-type body (bulk) SiO2 Thickness = tox ELEC6270 Fall 07, Lecture 5

  8. Gate Capacitance Cg = Cox WL = C0 , intrinsic cap. Cg = Cpermicron W εox Cpermicron = Cox L = ── L tox where εox=3.9ε0 for Silicon dioxide = 3.9×8.85×10-14 F/cm ELEC6270 Fall 07, Lecture 5

  9. Approx. Intrinsic Capacitances Weste and Harris, CMOS VLSI Design, Addison-Wesley, 2005, p. 78. ELEC6270 Fall 07, Lecture 5

  10. Low-Power Transistors • Device scaling to reduce capacitance and voltage. • Body bias to reduce threshold voltage and leakage. • Multiple threshold CMOS (MTCMOS). • Silicon on insulator (SOI) ELEC6270 Fall 07, Lecture 5

  11. Device Scaling • Reduced dimensions • Reduce supply voltage • Reduce capacitances • Reduce delay • Increase leakage due to reduced VDD / Vth ELEC6270 Fall 07, Lecture 5

  12. A Simplistic View • Assume: • Dynamic power dominates • Power reduces as square of supply voltage; should reduce with device scaling • Power reduced linearly with capacitance; should reduce with device scaling • Delay is proportional to RC time constant; R is constant with scaling, RC should reduce • Power reduces with scaling ELEC6270 Fall 07, Lecture 5

  13. Simplistic View (Continued) • What if voltage is further reduced below the constant electric field value? • Will power continue to reduce? Yes. • Since RC is independent of voltage, can clock rate remain unchanged? • Answer to last question: • Yes, if threshold voltage was zero. • No, in reality. Because relatively higher threshold voltage will delay the beginning of capacitor charging/discharging. ELEC6270 Fall 07, Lecture 5

  14. Consider Delay of Inverter VDD R In Out C t B t B Charging of C begins GND ELEC6270 Fall 07, Lecture 5

  15. Idealized Input and Output t f VDD Vth INPUT 0.5VDD tB = tfVth /VDD Gate delay 0.5VDD OUTPUT time tB 0.69CR ELEC6270 Fall 07, Lecture 5

  16. Gate Delay For VDD>Vth Gate delay = (tfVth/VDD) + 0.69RC – 0.5 tf = tf (Vth/VDD– 0.5 ) + 0.69RC For VDD ≤Vth Gate delay = ∞ ELEC6270 Fall 07, Lecture 5

  17. Approx. Gate Delay vs. VDD Gate delay 0.5t f 0.69RC 0.5t f 0 1 2 3 4 5 VDD/Vth ELEC6270 Fall 07, Lecture 5

  18. Power - Delay vs. VDD ~CVDD2 Power Gate delay 0.5t f 0.69RC With leakage 0.5t f 0 1 2 3 4 5 VDD/Vth ELEC6270 Fall 07, Lecture 5

  19. Optimum Threshold Voltage Vthcan be changed by varying doping level, oxide thickness and body bias. Vth = 0.7V Vth = 0.3V Delay Delay or Energy-delay product Energy-delay product 0 1 2 3 4 5 6 • VDD / Vth J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston, Springer, 1996, p. 26. ELEC6270 Fall 07, Lecture 5

  20. K(VDD+ Vthp) Vo Vi = 0 CL K(VDD –Vthn) Low-Voltage Inverter • Assumed always in saturation. • Modeled as ideal current source. VDD VDD VDD K(VDD+ Vthp) Vo Vo Vi Vi = VDD CL CL K(VDD –Vthn) ELEC6270 Fall 07, Lecture 5

  21. Power Supply Scaling VDD= 1V Vth≈ 0.35V 1.0 0.8 0.6 0.4 0.2 0.0 1.0 0.8 0.6 0.4 0.2 0.0 Vo Volts IDD mA VDD= 0.5V 0.0 0.2 0.4 0.6 0.8 1.0 Vi Volts J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, IEEE Press and Wiley-Interscience, 2004, p. 116. ELEC6270 Fall 07, Lecture 5

  22. Bulk nMOSFET Polysilicon + Vgs + Vgd + Gate Vds Drain Source W n+ n+ L p-type body (bulk) SiO2 Thickness = tox ELEC6270 Fall 07, Lecture 5

  23. Transistor in Cut-Off State Polysilicon gate SiO2 p-type body - - - - - - - - - - - - - - - - - - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vg < 0 ELEC6270 Fall 07, Lecture 5

  24. Threshold Voltage, Vth Polysilicon gate SiO2 p-type body + + + + + + + + + + + - Depletion region 0 < Vg < Vth + + + + + + + + + + + + + + + + + + + + + + + + + + Vth is a function of: Dopant concentration, Thickness of oxide Polysilicon gate SiO2 p-type body + + + + + + + + + + + + + + - • - - - - - - - - - - - - - - - - - - • Depletion region • + + + + + + + + + + + + + • + + + + + + ++ + + + + + Vg > Vth ELEC6270 Fall 07, Lecture 5

  25. Cutoff: Ids = 0 Polysilicon + Vgs + Vgd = 0 + Gate Vds = 0 Drain Source W n+ n+ L p-type body (bulk) SiO2 Thickness = tox ELEC6270 Fall 07, Lecture 5

  26. Linear: Ids = 0 Polysilicon + = Vgs Vgs + Vgd > Vth + Gate Vds = 0 Drain Source W n+ - - - - - - n+ L p-type body (bulk) SiO2 Thickness = tox ELEC6270 Fall 07, Lecture 5

  27. Linear: Ids Increases with Vds Polysilicon + Vgs > Vgd > Vth Vgs + Vgd + > Vth 0 < Vds < Vgs-Vth Gate Drain Source W n+ - - - - - - n+ L p-type body (bulk) SiO2 Thickness = tox ELEC6270 Fall 07, Lecture 5

  28. Saturation: Ids Independent of Vds Polysilicon + Vgd < Vth Vgs + Vgd 0 < Vds > Vgs- Vth + > Vth Gate Drain Source W n+ - - - - - - n+ L p-type body (bulk) SiO2 Thickness = tox ELEC6270 Fall 07, Lecture 5

  29. α-Power Law Model Vgs > Vth and Vds > Vdsat = Vgs – Vth (Saturation region): β Ids = Pc ─ (Vgs – Vth)α 2 where β = μCoxW/L, μ = mobility For fully ON transistor, Vgs = Vds = VDD: β Idsat = Pc ─ (VDD – Vth)α 2 T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas,” IEEE J. Solid State Circuits, vol. 25, no. 2, pp. 584-594, 1990. ELEC6270 Fall 07, Lecture 5

  30. α-Power Law Model (Cont.) 400 300 200 100 0 Shockley α-power law Simulation Idsat Ids (μA) Vgs = 1.8V 0 0.3 0.6 0.9 1.2 1.5 1.8 Vds ELEC6270 Fall 07, Lecture 5

  31. α-Power Law Model (Cont.) 0 Vgs < Vthcutoff Ids = Idsat × Vds/Vdsat Vds < Vdsatlinear Idsat Vds > Vdsatsaturation Vdsat = Pv (Vgs – Vth)α/2 ELEC6270 Fall 07, Lecture 5

  32. α-Power Law Model (Cont.) • α = 2, for long channel devices or low VDD • α ~ 1, for short channel devices ELEC6270 Fall 07, Lecture 5

  33. Power and Delay Power = CVDD2 CVDD11 Inverter delay = ──── (─── + ─── ) 4 Idsatn Idsatp KVDD = ─────── (VDD – Vth)α ELEC6270 Fall 07, Lecture 5

  34. Power-Delay Product VDD3 Power × Delay = constant × ─────── (VDD – Vth)α Power Delay 0.6V 1.8V 3.0V VDD ELEC6270 Fall 07, Lecture 5

  35. Optimum Threshold Voltage For minimum power-delay product: 3Vth VDD = ─── 3 – α For long channel devices, α = 2, VDD = 3Vth For very short channel devices, α = 1, VDD = 1.5Vth ELEC6270 Fall 07, Lecture 5

  36. Leakage VDD IG Ground R n+ n+ Isub IPT ID IGIDL ELEC6270 Fall 07, Lecture 5

  37. Leakage Current Components • Subthreshold conduction, Isub • Reverse bias pn junction conduction, ID • Gate induced drain leakage, IGIDL due to tunneling at the gate-drain overlap • Drain source punchthrough, IPT due to short channel and high drain-source voltage • Gate tunneling, IGthrough thin oxide ELEC6270 Fall 07, Lecture 5

  38. Subthreshold Leakage Vgs – Vth Isub = I0 exp( ───── ), where vT = kT/q = 26 mV n vT at 300K Ids 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA Saturation region Subthreshold region Vth 0 0.3 0.6 0.9 1.2 1.5 1.8 V Vgs ELEC6270 Fall 07, Lecture 5

  39. Normal CMOS Inverter VDD o output input GND SiO2 Polysilicon (input) output GND VDD metal 1 p+ n+ p+ p+ n+ n+ n-well p-substrate (bulk) ELEC6270 Fall 07, Lecture 5

  40. Leakage Reduction by Body Bias VBBp VDD o output input GND VBBn SiO2 Polysilicon (input) VBBn VBBp VDD output GND metal 1 p+ n+ p+ p+ n+ n+ n-well p-substrate (bulk) ELEC6270 Fall 07, Lecture 5

  41. Body Bias, VBBn Polysilicon gate SiO2 p-type body + + + + + + + + + + + - Depletion region 0 < Vg < Vth + + + + + + + + + + + + + + + + + + + + + + + + + + Vt is a function of: Dopant concentration, Thickness of oxide Polysilicon gate SiO2 p-type body - - - - - - - - - - - - - - - - - - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ++ + + + + + Vg < 0 ELEC6270 Fall 07, Lecture 5

  42. Further on Body Bias • Large body bias can increase gate leakage (IG) via tunneling through oxide. • Body bias is kept less than 0.5V. • For VDD = 1.8V • VBBn = - 0.4V • VBBp = 2.2V ELEC6270 Fall 07, Lecture 5

  43. Summary • Device scaling down reduces supply voltage • Reduced power • Increases delay • Optimum power-delay product by scaling down threshold voltage • Threshold voltage reduction increases subthreshold leakage power • Use body bias to reduce subthreshold leakage • Body bias may increase gate leakage ELEC6270 Fall 07, Lecture 5

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