Electronic system level Design Lab environment overview

1. Electronic system level DesignLab environment overview Speaker: 范辰碩

2. Outline • Overview of ESL design tool • Introduction of AndESLive

3. Overview of ESL design tool

4. ESL design tool • In this course, we adopt two ESL design tool in the lab. • CoWare • It provide a virtual platform to achieve a ESL design • use various component to combine a system level design, such as ARM CPU core, AHB,APB, user define IP and etc. • AndESLive • To provide a virtual platform to achieve a SoC/ESL design • Include Andes CPU core and various soft IP component

5. Introduction of AndESLive

6. Virtual SoC and software design flow

7. Andes Virtual Platform Andes Development Platform What is Virtual Platform? “It is a system-level simulation model that characterizes real system behavior. It operates at the level of processor instructions, function calls, memory accesses and data packet transfers, etc, as opposed to the bit-accurate, nanosecond-accurate logic transitions of a register transfer level (RTL) model.”

8. S/W Development with Andes Tools SW Developer Desktop (AndeSightTM) Other plug-in tools SOC Builder AndeSoftTM Profiler Debugger Applications Applications Integrated Development Environment Program Builder Middleware Middleware Operating Systems Operating Systems Compiler BSP/Device Drivers BSP/Device Drivers Assembler DEVICE SOFTWARE STACK Editor VEP (AndESLiveTM) AndESLiveTM/API Virtual I/O Connectivity

9. AndESLive™ VEP Environment • Cycle-accurate CPU simulation model • Speed: 30 MIPS • Pre-built IP models • Generic: dram controller, bus controller, DMA, GPIO, etc. • Controllers for LCD, MAC, USB, etc. • Virtual IO service to speed up simulation for non-focused modules • Customer’s IP models • Thru C++ interface • SoC Builder • Construct SoC thru GUI drag-and-drop • List memory/interrupt mapping for SW engineers