1 / 36

Microelectronics 2

Electrical Engineering 2. Lecture 17. Microelectronics 2. Dr. Peter Ewen. (Room G08, SMC; email - pjse). SMALL SIGNAL MODEL FOR FET’s. h 11. i 1. i 2. + -. h 12 v 2. h 21 i 1. v 1. v 2. 1/h 22. Fig. 104: Hybrid (or h-parameter) small signal equivalent circuit for a transistor.

xia
Download Presentation

Microelectronics 2

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Electrical Engineering 2 Lecture 17 Microelectronics 2 Dr. Peter Ewen (Room G08, SMC; email - pjse)

  2. SMALL SIGNAL MODEL FOR FET’s h11 i1 i2 + - h12v2 h21i1 v1 v2 1/h22 Fig. 104: Hybrid (or h-parameter) small signal equivalent circuit for a transistor h11 – resistance h12, h21 – dimensionless h22 – conductance For an FET, the input current i1 is extremely small: i1 = ig (gate current) 10-12A MOSFET  i1≈ 0

  3. SMALL SIGNAL MODELS FOR FET’s h11 i1 i2 i2 = ids g d + - h12v2 h21i1 gmvgs v1 = vgs v1 v2 v2 = vds 1/h22 rd s s rd – the drain resistance Fig. 105: Small signal equivalent circuit for a FET The small signal quantities ids, vgs represent small changes in the DC quantities: ids≡ ΔIDS vgs≡ ΔVGS idsΔIDS IDS = ≈ = gm - transconductance vgsΔVGS VGS  ids≈ gmvgs

  4. For MOSFET’s: The drain resistance, rd, is typically > 50 kΩ and accounts for the slope in the flat region of the output characteristics. For MOSFET:

  5. Common-source FET amplifier Fig. 106 VDD • voltage-divider • bias scheme ids RD R1 • input and output • signals coupled • in/out via capacitors vo d g • output taken from drain for common-source amplifier s ~ vi RS R2 CS • capacitor CS “short- circuits” RS for AC signals and ensures vi is dropped entirely between gate and source

  6. Common-drain FET amplifier Fig. 106 VDD • voltage-divider • bias scheme ids CD RD R1 • input and output • signals coupled • in/out via capacitors d g • output taken from source for common-drain amplifier s vo ~ vi RS R2 • capacitor CD “short- circuits” RD for AC signals

  7. Common-gate FET amplifier s Gate is common to input and output d vi g vo input output Fig. 106(c) VDD • voltage-divider bias • scheme ids • input and output signals • coupled in/out via capacitors RD R1 • input goes to source for common-gate amplifier, hence output taken from drain vo d g s vi • capacitor CG “short- circuits” R2 for AC signals and ensures vi is dropped entirely between gate and source CG ~ RS R2

  8. AC equivalent circuit for the common-source / common-drain FET amplifier Fig. 107 VDD To find the AC equivalent circuit: ids • replace all capacitors by short-circuits RD R1 vo • short-circuit the DC supply (cs) d g vo s (cd) ~ vi RS R2

  9. AC equivalent circuit for the common-source / common-drain FET amplifier Fig. 107 d g To find the AC equivalent circuit: ids gmvgs rd • replace all capacitors by short-circuits s s vo • short-circuit the DC supply (cs) d g RD vo • replace transistor with its small-signal model s R1||R2 (cd) ~ vi RS

  10. gmvgs rd AC equivalent circuit for the common-source / common-drain FET amplifier Fig. 107 d To find the AC equivalent circuit: ids • replace all capacitors by short-circuits s vo • short-circuit the DC supply (cs) d RD vo • replace transistor with its small-signal model s R1||R2 (cd) ~ vi RS

  11. LECTURE 17 THE BIPOLAR JUNCTION TRANSISTOR (BJT) • BJT fabrication process  BJT operation (npn device) • BJT carrier flows • Current amplification • BJT CB input characteristics

  12. base base emitter collector emitter collector n p n p n p The Bipolar Junction Transistor (BJT) npn (Discrete) Transistor Fabrication (e.g. BC107, 108, 109) base emitter base SiO2 epitaxial n-type layer n emitter p base 10m n collector n-type wafer n+ 200m Aluminium collector

  13. Fig. 110: Three different designs of BC108 transistor.

  14. Fig. 109 collector pin Al wires emitter pin base pin

  15. Fig. 111: interior of transistor package

  16. base emitter collector n p n • BJT’s should be connected as labelled, otherwise gains and breakdown voltages will be drastically reduced base emitter base n p 10m n • base is deliberately made thin, ~1 n+ 200m collector

  17. Energy bands for an npn transistor under zero applied bias Fig. 112 depletion regions emitter base collector n p n Conduction Band EF Electron Energy Valence Band

  18. Energy bands for an npn transistor under normal biasing conditions Conduction Band Valence Band Fig. 113 emitter base collector n p n VCB VBE + + electrons Electron Energy

  19. Carrier flows in an npn BJT n-type emitter p-type base n-type collector electrons α|IE| |IE| electrons ICBO holes holes holes (1-)|IE| Map of the Battle of Austerlitz

  20. Fig. 114 BJT CARRIER FLOWS (npn DEVICE)  - emitter efficiency α – common-base current gain n-type emitter p-type base n-type collector (lightly doped) α|IE| electrons |IE| IC IE electrons ICBO holes holes (1-)|IE| holes IC = αIE + ICBO base-emitter junction collector-base junction IB VCB VBE + +

  21. Current Amplification base emitter collector n p n IC IE IB Define: Common-emitter current gain Collector cut-off current Typically: ICBO~ 10-7 – 10-8 A ICEO~ 10-5 – 10-6 A ICBO doubles for every 10°C rise in temperature.

  22. 8. Temperature dependence of BJT parameters A Si BJT has β = 100 and ICBO = 10 nA at 25°C, and is used in the circuit below. Calculate IC at 25°C and 55°C if β = 150 at 55°C and VBE decreases by 2mV/°C. IC 1kΩ 1MΩ 30V 6V

  23. •α↑ as T↑ because at higher temperatures the electrons are moving faster and so take less time to cross the base • so there is less time for recombination to occur, and hence fewer electrons are lost through recombination • If the amount of recombination goes down, α↑ So β↑ since

  24. 8. Temperature dependence of BJT parameters IC 1kΩ 1MΩ 30V 6V IB At 25oC 0.7V

  25. IC 1kΩ 1MΩ 30V 6V IB At 55oC VBE VBE decreases by 2mV/°C. ICBO doubles for every 10°C rise. Note that IC has gone up by more than 50% (531μA →816μA) for this small temperature increase.

  26. COMMON BASE CONFIGURATION Fig. 115 (a) IE IC e c b INPUT VBE OUTPUT VCB IB INPUT CHARACTERISTICS OUTPUT CHARACTERISTICS IE(VBE) IC(VCB) n p n

  27. For diode: Fig. 116: Input Characteristic – CB Configuration IE / mA VCB = 0V VCB = 25V rd – dynamic resistance 10 8 6 4 2 0 For BJT: Increasing VCB re – dynamic emitter resistance For  = 1, T = 300 K and IE, IC in mA: 0 0.2 0.4 0.6 0.8 VBE / V

  28. IE ≈ IC VCB = 0V VCB = 25V IE / mA INPUT OUTPUT IE IC e c 10 8 6 4 2 0 b VBE VCB IB TRANSFER CHARACTERISTIC IC(VBE) Transconductance, gm, is slope of transfer characteristic, hence: 0 0.2 0.4 0.6 0.8 VBE / V

  29. 9. Dynamic Emitter Resistance Determine the dynamic emitter resistance and transconductance at 25°C and 55°C for the BJT in example 8. (Assume  = 1.)

  30. 9. Dynamic emitter resistance For  = 1, T = 300 K and IE, IC in mA: At 25oC At 55oC

  31. Summary • THE BIPOLAR JUNCTION TRANSISTOR • BJT FABRICATION (DISCRETE npn DEVICE) • n-type wafer used – • heavily doped to reduce collector resistance. • Thin epitaxial layer of lightly doped Si deposited on surface to increase breakdown voltage at collector-base junction. • p-type base and n-type emitter formed in epitaxial layer in usual way. • Al evaporated onto back of wafer to form collector • contact; Al contacts made to base and emitter on • surface. collector

  32. Base region deliberately made thin (~1m) to reduce recombination in base. • Device is NOT symmetrical with respect to interchange of emitter and collector. collector

  33. emitter base collector n p n VCB VBE + + • OPERATION – npn DEVICE • Under normal operation: • e-b junction is forward biased • c-b junction is reverse biased • Forward bias at e-b junction causes electrons to flow from emitter to base. • Electrons diffuse across base and are swept into collector by the field in the depletion region at collector-base junction. • Flow is very sensitive to height of the energy barrier, which depends on VBE .

  34. CARRIER FLOWS – npn DEVICE • Electrons diffuse across e-b junction and through base to collector. Most reach collector provided α ≈ 1. • Holes diffuse from • base to emitter. This • flow is small • provided  ≈ 1 • Holes enter base • from external • circuit to replenish • those used up in • recombination. • Small leakage current ICBO across reverse biased • collector-base junction: IC = αIE + ICBO

  35. CURRENT AMPLIFICATION • IC = βIB + ICEO [ ICEO = (1+β)ICBO ] • β = α/(1-α) – common-emitter current gain β, ICEO and VBE depend on temperature

More Related