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Improving Detactability of Resistive Open Defects in FPGAs

C. enter for. R. eliable. C. omputing. Improving Detactability of Resistive Open Defects in FPGAs. Mehdi Baradaran Tahoori and Edward J. McCluskey Center for Reliable Computing Stanford University. Outline. Problem Statement Introduction Resistive opens in ASICs FPGA Model Detection

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Improving Detactability of Resistive Open Defects in FPGAs

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  1. C enter for R eliable C omputing Improving Detactability of Resistive Open Defects in FPGAs Mehdi Baradaran Tahoori and Edward J. McCluskey Center for Reliable Computing Stanford University

  2. Outline • Problem Statement • Introduction • Resistive opens in ASICs • FPGA Model • Detection • New Techniques • Path Delay Analysis • Simulation Results • Summary

  3. Statement of Problem • Problem addressed • Detection of resistive open defects • In FPGA interconnect network • Resistive opens • Increase circuit delay • Do not change signal values • Need at-speed testing

  4. Statement of Results • Improving detectability • By magnifying effect of the defect • Up to 12x increase • Detection at lower speeds • Techniques • Increase fanout load • Increase wire load capacitance

  5. Resistive Opens • Imperfect connection between two circuit nodes • Defect resistance • Causes: • Imperfect Contact • Imperfect Via • Thin Wire

  6. Modeling of Resistive Opens • Delay of defective transistor • Falling transition • Rtr(VDD): Transistor turn-on resistance • Function of VDD

  7. Terminology • Delay Delta • Delay Ratio • Higher delay ratio  Higher detection resolution

  8. Outline • Problem Statement • Introduction • Resistive opens in ASICs • FPGA Model • Detection • New Techniques • Path Delay Analysis • Simulation Results • Summary

  9. Xilinx Virtex FPGA Model Logic block CLB IO Mux Switch Matrix (SM) Line Segments

  10. Switch Matrix N2 N3 N1 SRAM Buffer W1 E1 E2 W2 Programmable Interconnect Point (PIP) E3 W3 S3 S1 S2

  11. PIP • Programmable Interconnect Point • Two types of PIPs in each switch matrix • Buffered PIP • Pass transistor + buffer • Connected to longer wires • Faster • Unbuffered PIP • Only pass transistor • Connected to shorter wires • Less area

  12. Issues in FPGA Testing • Circuit is Reprogrammable • Lots of available unused routing resources • 5-10% routing resource utilization • Even with 100% logic utilization • Controllable parameters • Test voltage • Test temperature • Test frequency • Load capacitance

  13. Modeling of FPGA • Simple routing path • PIP and logic blocks • Input and output stages of logic blocks • Inverter buffers (next slide) IN OUT Logic block Switch Matrix

  14. SPICE Simulation of FPGA Model • TSMC 0.18 technology • Various voltages and defect resistances • Nominal supply voltage: 2.5 V Inside Switch Matrix

  15. Dependence of Delay on VDD * Nominal

  16. Dependence of Delay Ratio on VDD * Nominal

  17. Conclusion • Consistent with simulation results for ASICs • Higher VDD Higher delay ratio • Increase in delay ratio • Less than 5%

  18. New Technique for Delay Ratio • Increase load capacitance • Additional fanout paths • Unused PIPs • Increased delay ratio OUT IN A B C Logic block Switch Matrix

  19. Circuit Model • One additional fanout • Turning on one more PIP • Maximum number of fanouts • Number of PIPs connected to A A

  20. Dependence of Delay on Fanout

  21. Dependence of Delay Ratio on Fanout

  22. SPICE Simulation Results • Nominal voltage • Significant increase in delay ratio • Improvement scalable • with number of additional branches • More delay ratio for larger defects • Detection at lower tester speed !

  23. Path Delay Analysis • Effect of Path length on delay ratio • Two cases • Unbuffered PIPs • Pass transistor • Buffered PIPs • Pass transistor + Inverter

  24. Unbuffered PIPs • Simulation for various path lengths • One additional fanout

  25. Delay Ratio • No fanout

  26. Delay Ratio • One additional fanout in 1st stage

  27. Improvement • For various path length

  28. Buffered PIPs • Simulation for various path lengths • One fanout

  29. Delay Ratio • No fanout

  30. Delay Ratio • One additional fanout in 1st stage

  31. Improvement

  32. More Increase in Delay Ratio • Using line segment loads in additional fanouts • For unbuffered PIPs • Increase in total load capacitance • Stages not isolated OUT IN B A C Logic block Switch Matrix

  33. Circuit Model • Wire • RC network • Lumped model

  34. SPICE Simulation Setup • TSMS 0.18 m technology • Two kinds of wires • Short Wire (100 m) • Single lines in FPGA • Rw = 10 , Cw = 43 fF • Long wire (1.4 mm) • Hex and long lines in FPGA • Rw = 140 , Cw = 615 fF

  35. Effect of Wire Load on Delay

  36. Effect of Wire Load on Delay Ratio

  37. Simulation Results • Increase in delay ratio • Scalable • Proportional to number of fanouts • Non-sensitive to path length • Almost same improvement • Unbufferd PIPs • Better results • Capacitance of extra line segments

  38. Summary • Detection of resistive opens in FPGAs • Increase load capacitance • Additional fanouts • For buffered PIPs • + Line segment loads in fanouts • For unbufferd PIPs • Scalability • Path Delay Analysis

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