GGT-Electronics System design

1. GGT-Electronics System design Alexander Kluge CERN-PH/ED April 3 , 2006

2. General: Chip Specifications Calculation,simulation Working parameters A. Kluge

3. General: Chip Specifications A. Kluge

4. I/O block diagram of chip inputs output A. Kluge

5. I/O of chip • Which connections to on-detector electronics? • 2 Power supplies per chip: • Core supply; analog and digital (1.5V / 1.3A / 2W) • I/O supply (≤ 2.5V / ~0.1A) • Several wire pads (~30) but all to few conductors outside • Outputs (5 Gbits/s) • Data: ≥ 2 high speed serial outputs (differential 3 Gbit/s) • Status: 1 low speed serial output pair • (6 pads) • Inputs • Clock input: 1 differential pair • Configuration & control: 1 low speed serial output pair • 2 single ended control • 8 config • (6 + 8 pads) A. Kluge

6. I/O block diagram of chip 1 1 1 VddCoreDig VddCoreAna 5 5 5 VddIO 2 2 2 2 clk data0 2 2 2 2 control data1 2 2 status 2 2 control 10 8 test config GndCoreAna 5 5 5 GndIO GndCoreDig 1 A. Kluge

7. Configuration A. Kluge

8. Readout and supply Chip size Readout and supply 3 mm • Readout needs possibly more space ->not leaving 18mm active area • Supply from one side has strong power drop • Thinning of long narrow chips more difficult 18 mm 21 mm A. Kluge

9. Highest rate Configuration A. Kluge

10. Configuration Max rate on one chip, but chip smaller A. Kluge

11. Configuration: study starting point A. Kluge

12. Components in beam of 48 x 36 mm Carbon; 48 x 36 mm2; 100 µm Si; 48 x 12 mm2; 200 µm Si; 9.6 x (12+6) mm2; 100 µm 48 x 9 mm2;Al; 50 µmKapton; 50 µm + 12 µm Al; 10 µm * 50% Al bonds; 2mm; 25 µm SMD comp 0402 (glued or wire bonded); 1 x 0,5 x 0.5 mm3 A. Kluge

13. Low mass cable 9 mm A. Kluge

14. 9 mm: 0.69% 3 mm: 0.69% 3 mm: 0.58% 6 mm: 0.48% 3 mm: 0.58% 3 mm: 0.69% 9 mm: 0.69% Configuration • Center: 0.45% X0 • Off Center1: 0.55% X0 • Off Center2: 0.65% X0 • Border: 0.65% X0 • Sensor&bonds: 0.24% X0 • RO chip: 0.11% X0 • Low mass cable: 0.10% X0 • Structure: 0.10% X0 A. Kluge

15. Configuration: study starting point A. Kluge

16. Signal lines 100µm width200µm pitch + separation =>~ 0.7 mm per signal line • Vdd lines 1mm & separation =>~1.2 mm • Per chip and side:3 Vdd + 3 signal =>5.7 mm 9 mm A. Kluge

17. Configuration • Sensor&bonds: 0.24% X0 • RO chip: 0.11% X0 • Low mass cable: 0.10% X0 • Structure: 0.10% X0 A. Kluge

18. Conclusion: configuration • What is the required material budget? • Is the starting point configuration acceptable and if not what are the reasons? • Use reasons to adapt other parameters accordingly - geometric efficiency (areas of complete inefficiency),electronics efficiency, beam geometry A. Kluge

19. Number of components needed • 3 stations each consisting of: • 1 module & mechanics & cooling • 1 modules consists of: • 3 assemblies9 assemblies needed for GGT • 100 days of operation: • Life time of assembly : 14 to 28 days => • 4 to 7 exchange cycles • 36 to 63 assemblies needed • in this scheme 4 low mass cables are needed for 1 module => in total 48 to 84 low mass cables needed A. Kluge

20. A. Kluge

21. Configuration 3 x 5 • Assume matrix of 40 rows x 32 columns: • 12 mm x 9.6 mm = 115.2 mm2 • Chip size • (12 + (2 x 3mm)) x 9.6 mm = 18 x 9.6 mm • Pixel size 300 um x 300 um • => 40 x 32 pixels = 1280 pixels • Max. Avg Rate of column in center chip: ~150 MHz/cm2 (for beam with max. 173 MHZ/cm2) • => 135 kHz/pixel • => 173 MHz/chip • => 173 MHz/chip * ~32 bit = 5.5 Gbit/s A. Kluge

22. Configuration 3 x 4 • Assume matrix of 40 rows x 40 columns: • 12 mm x 12 mm = 144 mm2 • Chip size • (12 + (2 x 3mm)) x 12 mm = 18 x 12 mm • Pixel size 300 um x 300 um • => 40 x 40 pixels = 1600 pixels • Max. Avg Rate of center chip: ~150 MHz/cm2 (for beam with max. 173 MHZ/cm2) • => 135 kHz/pixel • => 216 MHz/chip • => 216 MHz/chip * ~32 bit = 6.9 Gbit/s A. Kluge

23. Column of 40 pixels Rate and super pixels • Super pixel structure for rate maximum in center Readout and supply • 12 mm column centered on beam~150 MHz/cm2 => 135 kHz/pixel => 99%, • Td = 10ns, N=7, Nseg = 183; • Td = 6 ns, N= 12, Nseg = 107; • Td = 7.4 ns, N= 10, Nseg = 128; Readout and supply A. Kluge

24. Column of 40 pixels Rate and super pixels • Super pixel structure for rate maximum in center Readout and supply • 12 mm column centered on beam~150 MHz/cm2 => 135 kHz/pixel => 98%, • Td = 10ns, N=14, Nseg = 91; • Td = 6 ns, N= 24, Nseg = 53; • Td = 7.4 ns, N= 20, Nseg = 64; Readout and supply A. Kluge

25. Read out • 3 planes x 3 x 5 chips x (2 high speed + 2 low speed + 1 clock) optical links = 90 high speed links +90 low speed links+ 45 clock links A. Kluge

26. ALICE pixel trigger processor FPGA config HS119 JTAG JTAG Parallel data bus parallel bus CTP parallel bus Control serial link HS109 Multi Gigabit serial link OPTIN9 HS108 Multi Gigabit serial link SPD RO clk FPGA config HS11 JTAG Parallel data bus TTC TTC parallel bus Control serial link DDL DAQ data link HS1 Multi Gigabit serial link OPTIN0 control & data HS0 Ethernet BRAIN to computer (control room) 12 x 800 MHz A. Kluge

27. Conclusion • Configuration specification have influence on chip and system design • Full information and choice of options only during design of full chip A. Kluge