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SYSTEM INTEGRATION MODULE (SIM)

SYSTEM INTEGRATION MODULE (SIM). Module Objectives. Understand Reset handling performed by SIM Understand Interrupt handling performed by SIM Configure control registers for your system Module exercise:

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SYSTEM INTEGRATION MODULE (SIM)

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  1. SYSTEM INTEGRATIONMODULE(SIM)

  2. Module Objectives • Understand Reset handling performed by SIM • Understand Interrupt handling performed by SIM • Configure control registers for your system • Module exercise: As part of reset servicing, determine which reset occurred and call an appropriate reset recovery routine.

  3. IRQ LVI Direct Memory Access Module (DMA) System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) 68HC08 CPU RESET COP BREAK Internal Bus (IBUS) Random Access Memory (RAM) Serial Peripheral Interface (SPI) Electronically Programmable ROM Monitor ROM Serial Communications Interface (SCI) System Integration Module • Derives Bus clocks from CGM • Bus clock generation and control for CPU and peripherals • Stop/wait/reset/break entry and recovery • Internal clock control • Master reset control, including power-on reset (POR) and COP timeout • Interrupt control: • Acknowledge timing • Arbitration control timing • Vector address generation • CPU enable/disable timing • Modular architecture expandable to 128 interrupt sources

  4. SIM Block Diagram MODULE STOP MODULE WAIT CPU STOP (FROM CPU) STOP/WAIT CONTROL CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) SIM COP CLOCK COUNTER CGMXCLK (FROM CGM) CGMOUT (FROM CGM)  2 CLOCK CLOCK GENERATORS INTERNAL CLOCKS CONTROL L VI (FROM LVI MODULE) RESET POR CONTROL PIN LOGIC MASTER ILLEGAL OPCODE (FROM CPU) RESET PIN CONTROL RESET ILLEGAL ADDRESS (FROM ADDRESS CONTROL MAP DECODERS) SIM RESET STATUS REGISTER COP (FROM COP MODULE) RESET INTERRUPT SOURCES INTERRUPT CONTROL AND PRIORITY DECODE CPU INTERFACE

  5. System Integration Module- Bus Clocks - • Takes output of Clock Generation Module • Distributes clocks to submodules • Controls system clocks in low power modes • WAIT • Stops clock to CPU only • STOP • Stops all bus clocks • Asserts SIMOSCEN • Shuts down CGM oscillator circuit

  6. READ: POR PIN COP ILOP ILAD 0 LVI 0 SRSR WRITE: RESET: 1 0 0 0 0 0 0 0 Reset Source Bit cleared by Reading SRSR or Power On Reset Reset Control SIM Reset Status Register • The SRSR records the cause of the last reset sequence. (One and only one bit will be set!) • MCU Reset Sources: • Power-on Reset Module (POR) • External Reset Pin (RST) • Illegal Opcode Reset • Illegal Address Reset • Caused by an opcode fetch from an illegal address • Low-Voltage Inhibit Module (LVI) • Computer Operating Properly Module (COP)

  7. Power On Reset OSC1 PORRST 4096 32 32 CYCLES CYCLES CYCLES CGMXCLK CGMOUT RST IAB $FFFE $FFFF • Voltage on VDD changes from logic zero to logic one • Internal reset signal is asserted • Issues • All internal clocks to CPU and Modules are held inactive for 4096 CGMXCLK clock cycles • Allows for stabilization of oscillator • RST pin is driven low during stabilization of oscillator • Power On Reset(POR) bit in SIM reset status register is set and all other bits in register are cleared.

  8. Power-On Reset Flow Vdd Internal clocks held Low for 4096 CGMXCLK clock cycles POR Pulse RESET pin is driven low Reset pin is released. Oscillator begins operating

  9. External Pin Reset CGMOUT RST IAB PC VECT H VECT L • Internal reset signal can be generated by pulling RST* pin low • PIN bit of the SIM reset Status Register (SRSR) is set if: • RST* held low for a minimum of 67 CGMXCLK cycles • PIN Bit Set Timing: • POR/LVI Resets 4163 = (4096 +64 + 3) Cycles • All Other Resets 67 = (64+3) Cycles

  10. Internal Resets ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET LVI • Illegal Opcode Reset • Occurs when CPU decodes instruction not in opcode map • Illegal Address Reset • Occurs when CPU tries to fetch an instruction from an address not in defined memory map • Low Voltage Inhibit Reset • LVI indicates VDD dropped below preset limit • Reset remains for 4095 CGMXCLK clock cycles after VDD is restored • Allows clock to stabilize • Computer Operating Properly Reset • COP indicates it’s timer has expired • Timer must be periodically reset • System protection, prevents runaway processors POR

  11. Internal Reset Timing IRST RST PULLED LOW BY MCU RST 32 CYCLES 32 CYCLES CGMXCLK IAB VECTOR HIGH

  12. Internal Reset Flow Internal Reset Signal is issued RST is actively driven low for 16 bus cycles Internal reset signal is asserted for 16* additional bus clocks *This is longer for LVI Reset RST pin is tested RST pin low indicates that an external reset has occurred RST pin high indicates that an internal reset occurred and the appropriate internal reset bit is set

  13. Interrupts • 68HC08 can process up to 128 separate resets/interrupts • On-chip peripheral modules generate maskable interrupts • Recognized only if interrupt mask bit clear • Indicated by an interrupt status flag, also • All interrupts are prioritized • SIM module • Receives all interrupts • Performs arbitration • Passes highest priority interrupt on to CPU

  14. Local GlobalFunction Mask Mask Priority Vector Address Resets (6/1) No None 1 $FFFE - $FFFF Software No None 2 $FFFC - $FFFDInterrupt IRQ1 Yes I-bit 3 $FFFA - $FFFB PLL Interrupt Yes I-bit 4 $FFF8 - $FFF9 DMA Yes I-bit 5 $FFF6 - $FFF7Interrupts (3/1) Timer Yes I-bit 6 $FFEC - $FFF5Interrupts (5/5) SPI Interrupts (2/2) Yes I-bit 7 $FFE8 - $FFEB SCI Yes I-bit 8 $FFE6 - $FFE7Interrupts Yes I-bit 9 $FFE4 - $FFE5(8/3) Yes I-bit 10 $FFE2 - $FFE3 IRQ2/Keyboard Yes I-bit 11 $FFE0 - $FFE1 68HC708XL36 InterruptSources and Priorities

  15. SIM Exercise • Write a code sequence that determines what the last reset was and then calls an appropriate subroutine that implements a reset recovery scheme. • The details of the called routines is not important. • Given: • * Reset service/recovery caller • ORG $FE01 • SRS RMB 1 • JMPTBL FDB PONRCVY • FDB PINRCVY • FDB COPRCVY • FDB ILOPRCVY • FDB ILADRCVY • FDB LVIRCVY

  16. Additional Information- Low Power Modes - • WAIT Mode Control • SIM stops CPU system clock • Peripheral clocks continue to run • Clears I-bit in CCR • Exit conditions • Non-masked external interrupt • Any non-masked internal interrupt • Module must also be active • Any Reset

  17. Additional Information- Low Power Modes - • STOP Mode Control • SIM Counter is reset and system clocks are disabled • SIM disables clock generator outputs (CGMOUT and CGMXCLK) • CPU and Peripherals are stopped • Clears I-bit in CCR • Exit conditions • Non-masked external interrupt • External Reset only • Recovery time is selectable • normal delay 4096 CGMXCLK cycles or • If SSREC = 1 in MOR(masked option register) delay 32 CGMXCLK cycles • Ideal for applications using canned oscillators not requiring long start-up times

  18. READ: SBSW SBSR • RESERVED RESERVED NOTE1 WRITE: RESET: 0 1. Writing a logic zero clears SBSW Additional Information- Break Status and Control - • SIM Break Status Register (SBSR • SIM Break Stop/Wait (SBSW) status bit • Useful in applications requiring a return to a wait or stop mode after exiting from a break interrupt 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt

  19. Additional Information- Break Status and Control - READ: • SIM Break Flag Control Register (SBFCR) • Enables software to clear status bits by accessing status registers while the MCU is in a Break state • SIM Break Clear Flag Enable bit • To clear status bits during the break state, the BCFE bit must be set 1 = Status bits clearable during break 0 = Status bits not clearable during break • RESERVED SBFCR BCFE WRITE: RESET: 0

  20. READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD MOR WRITE: RESET: UNAFFECTED BY RESET Additional Information- Stabilization Delay - • Mask Option Register (MOR) • Short Stop Recovery • Selects either a long or short clock stabilization delay is to be used when exiting STOP 1 = Short stabilization delay (32 CGMXCLK clocks) • For CAN Oscillator - off Board 0 = Long stabilization delay (4096 CGMXCLK clocks) • On-board Oscillator

  21. READ: POR PIN COP ILOP ILAD 0 LVI 0 SRSR WRITE: RESET: 1 0 0 0 0 0 0 0 Reset Source Bit cleared by Reading SRSR or Power On Reset Register Summary READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD MOR WRITE: RESET: UNAFFECTED BY RESET

  22. SIM Exercise Solution * Reset service/recovery caller ORG $FE01 SRS RMB 1 Reset LDHX #JMPTBL ;Load base address of Jump table LDA SRS ;Read Reset Status Register CMP #$80 ;LVI Reset? BEQ DONE ;If so branch AIX #2 ;Offset = 2 CMP #$40 ;External Reset? BEQ DONE ;If so branch AIX #2 ;Offset = 4 CMP #$20 ;COP Reset? BEQ DONE ;If so branch AIX #2 ;Offset = 6 CMP #$10 ;ILOP Reset? BEQ DONE ;If so branch AIX #2 ;Must be ILAD Reset, Offset = 8 DONE JSR ,X • • • • JMPTBL FDB LVIRCVY FDB PINRCVY FDB COPRCVY FDB ILOPRCVY FDB ILADRCVY

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