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ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices

ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices. XOR, Parity Circuits, Comparators. Exclusive OR and Exclusive NOR Gates. XOR : XNOR :

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ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices

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  1. ECE 3110: Introduction to Digital SystemsChapter 6Combinational Logic Design Practices XOR, Parity Circuits, Comparators

  2. Exclusive OR and Exclusive NOR Gates • XOR : • XNOR : • Truth Table : XOR X Y XOR XNOR 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1 XOR X F Y X F Y

  3. XOR and XNOR Symbols • Equivalent Symbols of XOR gate • Equivalent Symbols of XNOR gate Any 2 signals (inputs or outputs) may be complemented without changing the resulting logic function

  4. SSI XOR and XNOR • 74x86 : 4 XOR gates • 74x266: 4 XNOR gates with “open collector” or “open drain” output

  5. I0 I0 I1 EVEN I1 I2 ODD I2 I3 I3 XOR Application: Parity Circuit • Odd Parity Circuit : The output is 1 if odd number of inputs are 1 • Even Parity Circuit : The output is 1 if even number of inputs are 1 • Example : 4-bit Parity Circuit Daisy-Chain Structure Tree structure Input : 1101 Odd Parity output : 1 Even Parity output : 0 EVEN ODD

  6. MSI Parity Circuit : 74x280

  7. Parity-Checking Application: memory

  8. Comparators • Compares Two binary words and indicate if they are equalMagnitude Comparators : Comparator A A=B? B A=B A Comparator A>B B A<B

  9. 4-bit comparator EQ_L Equality Comparators • 1-bit comparator

  10. Iterative Comparator

  11. Multi-bit Iterative Comparator

  12. MSI Comparator : 74x85 • 4 bit comparator • 3 outputs : A=B, A<B, A>B • 3 Cascading inputs • Functional Output equations : (A>B OUT)= (A>B)+(A=B).(A>B IN) (A<B OUT)= (A<B)+(A=B).(A<B IN) (A=B OUT)= (A=B).(A=B IN) • Cascading inputs initial values : (A=B IN) =1(A>B IN) =0(A<B IN) =0 74x85 A<BIN A<BOUT A=BIN A=B OUT A>BIN A>BOUT A0 B0 A1 B1 A2 B2 A3 B3

  13. 8 bit Comparator +5V 74x85 74x85 A<BIN A<BOUT A<BIN A<BOUT A<B A=BIN A=B OUT A=BIN A=B OUT A=B A>BIN A>BOUT A>BIN A>BOUT A>B A0 A0 A4 A0 B0 B0 B4 B0 A1 A1 A5 A1 B1 B1 B5 B1 A2 A2 A6 A2 B2 B2 B6 B2 A3 A3 A7 A3 B3 B3 B7 B3 Least Significant bits Most Significant bits

  14. 8-bit Magnitude Comparator

  15. Other conditions

  16. Next… • Adders, subtractors, ALUs • Reading Wakerly CH-6.10-6.11

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