Methodology and Use of Transactions for Advanced Functional Verification

1. Methodology and Use of Transactions for Advanced Functional Verification Mark Glasser Verification Technologist

2. Agenda • Mixed Abstractions are the real problem • Using transactions to specify design intent • Building transaction level environments • Intro to the AVM • Summary

3. Transaction Level 2000+ Register Transfer Level 1990+ 1980+ Gate Level Physical Level 1970+ Complexity and Abstraction • Moore’s Law drives higher design complexity • Each decade brings new abstractions to deal with increased complexity • Currently shifting from RTL to TLM

4. Designs are built by multiple teams Different disciplines Different perspectives Different modeling requirements Communication between teams must be efficient Verification Stakeholders SW Engrs SoC Architects Verification Engrs HW Engrs

5. Performance A C D Function Call B A Generic CPU (B, C and ctrl) Transaction TLM Channel D Mem A Specific CPU - ISS (B, C and ctrl) Bus Clock D Mem

6. Text, UML C, C++, Matlab SystemC SystemVerilog Design and Verification Languages Requirements Algorithm SoC Architecture RTL Verification RTL Design Verilog, VHDL Only Common Methodologies and Integrated Tools can make these work together

7. Mix & Match • Typically, in one simulation, we integrate • many abstraction levels • many models of computation • many language domains SystemC SystemVerilog PSL Testbench SystemC Wrapper SystemC Wrapper VHDL DUT Verilog DUT Emulator DUT Testbench C++ algorithm ISS Model

8. Essential Verification Design Intent Observed Behavior = ? Does design intent match observed behavior?

9. Design Intent • Design representation is well understood… • How to represent intent? • Must be easier/faster to build than the design • Must be at a higher abstraction level than the design • Must communicate with the design

10. TLM is Obvious Choice • High level of abstraction • Less detail means faster/easier to write and debug • Communicate to design via transactors • TLM standards enable reuse and IP interchange • Well known modeling languages support TLM • Models can be shared between architects, sw engineers, verification engineers, and hw engineers

11. TLM and Verification • All advanced verification methodologies today are based on transactions • Aids reuse • Representing transactions as classes makes randomization easier • Golden Models and Scoreboards are TLMs • Verification engineers have been producing TLMs for years without realizing it • Refinement and Abstraction • Refinement speeds up verification timescales • Abstraction speeds up testbench execution times

12. Golden Models ENV TRANSACTOR BLOCK TRANSACTOR ENV MONITOR MONITOR Transaction level stimulus and response • Golden Models are TLMs of expected behavior • Environments are (stochastic) models of external environment • Verification Engineers have been writing TLMs for years GOLDEN MODEL

13. Transaction Level Model ENVIRONMENT • Stimulus • Response • Coverage • Analysis SOFTWARE BLOCK 1 BLOCK 2 CPU TRANSACTION LEVEL BUS

14. Refinement – TL Bus • Begin verification before RTL is finished. • Refine as RTL comes on line • Increase execution speed by abstracting away RTL not being tested ENVIRONMENT SOFTWARE BLOCK 1 TRANSACTOR BLOCK 2 TRANSACTOR CPU TRANSACTION LEVEL BUS

15. Refinement – Pin Level Bus SOFTWARE ENVIRONMENT BLOCK 1 TRANSACTOR CPU TRANSACTOR BLOCK 2 MONITOR TRANSACTOR

16. Methodology TLM Based Verification Methodology Verification Methodology TLM Methodology

17. AVM Layering Test Controller Control UntimedTransactions Testbench-Specific Coverage Collectors Scoreboards Golden Models Performance Analyzers Analysis Untimed orPartially-timedTransactions Design-Specific StimulusGenerators Masters Slaves Environment Transactions Drivers Monitors Responders Protocol-Specific Transactors Pins DUT

18. AVM Architecture Scoreboard Transaction Level Components Coverage Test Ctrlr Monitor Monitor Transactors Stimulus Gen Driver DUT Resp- onder Slave

19. AVM • TLM provides a means to codify design intent • higher level of abstraction • Golden models are TLMs anyway • Decision making and analysis is done using untimed TLMs • Environment can communicate with DUT via transactors • TLM standards enable reuse

20. System Level Verification • Integrating blocks and subsystems • different levels of abstraction • different language domains • Reusing environment and testbench • across designs • across abstraction; through refinement process • Design exploration at high levels of abstraction • models run fast • models can be written relatively quickly • Verify assumptions and results at lower levels of abstraction

21. Summary • TLM standards enable Mentor’s AVM • Mentor’s AVM enables System Level Verification • AVM enables productivity increases by • parallelizing HW design, software development, and verification • reuse of verification components • sharing models amongst teams