640 likes | 970 Views
Structure and Physical Operation I -V characteristics MOSFET DC circuits CMOS Inverter MOSFET amplifiers Biasing MOSFETS High Frequency MOS model SPICE MOSFET model parameters. Chapter 4. MOSFET ID-VG, ID-VDS. Output Charc. Input Charc.
E N D
Structure and Physical Operation I -V characteristics MOSFET DC circuits CMOS Inverter MOSFET amplifiers Biasing MOSFETS High Frequency MOS model SPICE MOSFET model parameters Chapter 4
MOSFET ID-VG, ID-VDS Output Charc. Input Charc. IDsat = n Cox W/L (VGS - VTN)2/2 --- SQUARE LAW L>250nm
MOS Transistor Operating Regions VDD VDD
Triode or Linear Region OFF VGS < VT or VTO
Cgs ON/Triode: V > 0 or VGS > VTO Cgs = WL Cox; V > VDS OFF: V < 0 or VGS < VTO Cgs WL Cox Sat: V < 0 or VGS < VTO Cgs = 2/3 WL Cox ; V < VDS NMOS N Diffusion PMOS P Diffusion PolySilicon
SPICE MODEL parameters Over 200 parameters define Modern 65nm MOSFETs 2000nm
ID vs. VGS; VDS > V L > 250nm Square Law L < 250nm Vel. Sat.
ID vs. VGS; VDS > V Supplemental Taking the square root of ID and solving for slope & intercept; Extract VTO and KP
Enhancement/ Depletion Mode NMOS – 1st Quadrant PMOS – 3rd Quadrant Enhancement VTN > 0V VTP < 0V Depletion Mode VTN > 0V VTP < 0V
MOSFET parameters Ex -graphical ; V < VDS ID= W/LnCox (VGS - VTN)2/2 --- Sat. n Cox W/L = ID = W/L n Cox {V VDS + VDS2/2}---Triode or Lin Region
CMOS Inverter – Strong pull up & down Rise time Fall Time
INVERTER POWER Supplemental
The Digital CMOS inverter Supplemental
CMOS Logic NMOS pull dwn Zbar = AB+CD
CMOS Logic PMOS pull UP Z = A’+B’ C’+D’
CMOS Logic PMOS pull UP Z = A’+B’ C’+D’
CMOS Logic PMOS pull UP Z = A’+B’ C’+D’ Supplemental
CMOS Logic Supplemental
CMOS Logic & Scaling If CL 3 minimum loads or 7.5fF 1/2 um process OR 0.25fF 90nm process tr & tf equal?
CMOS Logic & Scaling > 300X less Pwr
CMOS Logic NMOS pull DWN Z’ = A(D+E) + (BC) PMOS pull UP Z = [A+(D E)] (B+C) PMOS pull UP Z = A’+B’ + C Supplemental NMOS pull DWN Z’ = ABC
CMOS Analog ID vs. VDS Early Voltage and Lambda Take Away – effective output resistance Modeled by 1/ID or VA/ID
ID vs. VGS - ID vs. VDS; Amplification
ID vs. VGS - ID vs. VDS; Amplification
Q pt Bias Stabilization Amplification
Q pt Bias Stabilization Amplification
f1 Bias Considerations Amplification
f2 Considerations Amplification
Common Source Summary • Select Qpt = (VGS, ID, & VDS)and estimate gm and gds =ID/VA • Stabilize the Bias or Quiescent point – VGG =VGSQ + ID RS • RG1, RG2 and RS VGG =VDD RG1/{RG1|| RG2} • Determine Cc1, Cc2, CS • Determine RD after finding gm and gds. • gain = -gm RD||rds||RL mid band gain • Generally – RL >> RD or rds & RG = RG||RG >> Rgen
Common Source Summary``
Why CMOS Inverter NMOS PMOS
Modeling rout Supplemental
Misc. Effects Supplemental
Shifting the Qpt for Gain A Gain A = ΔVDS/ ΔVGS
Distorting the Signal Distortion
Shifting the Qpt con’t Analytical ΔID ΔVGS gm = ΔID/ ΔVGS
MOSFET DC BIAS-CS,CD,CG Gain – modest Rin – High Ro – High Inverting Gain – modest Rin – low Ro – High noninverting Gain –Unity Rin – High Ro – Low Noninverting buffer