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Chapter 4

Structure and Physical Operation I -V characteristics MOSFET DC circuits CMOS Inverter MOSFET amplifiers Biasing MOSFETS High Frequency MOS model SPICE MOSFET model parameters. Chapter 4. MOSFET ID-VG, ID-VDS. Output Charc. Input Charc.

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Chapter 4

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  1. Structure and Physical Operation I -V characteristics MOSFET DC circuits CMOS Inverter MOSFET amplifiers Biasing MOSFETS High Frequency MOS model SPICE MOSFET model parameters Chapter 4

  2. MOSFET ID-VG, ID-VDS Output Charc. Input Charc. IDsat = n Cox W/L (VGS - VTN)2/2 --- SQUARE LAW L>250nm

  3. MOS Structure

  4. MOS Transistor Operating Regions VDD VDD

  5. MOS Transistor Operation-OFF

  6. Triode or Linear Region OFF VGS < VT or VTO

  7. Increasing VDS – ID saturates

  8. Cgs ON/Triode: V > 0 or VGS > VTO Cgs = WL Cox; V > VDS OFF: V < 0 or VGS < VTO Cgs  WL Cox Sat: V < 0 or VGS < VTO Cgs = 2/3 WL Cox ; V < VDS NMOS N Diffusion PMOS P Diffusion PolySilicon

  9. Significant Process Parameter Constants

  10. SPICE MODEL parameters Over 200 parameters define Modern 65nm MOSFETs 2000nm

  11. ID vs. VGS; VDS > V L > 250nm Square Law L < 250nm Vel. Sat.

  12. ID vs. VGS; VDS > V Supplemental Taking the square root of ID and solving for slope & intercept; Extract VTO and KP

  13. Enhancement/ Depletion Mode NMOS – 1st Quadrant PMOS – 3rd Quadrant Enhancement VTN > 0V VTP < 0V Depletion Mode VTN > 0V VTP < 0V

  14. MOSFET parameters Ex -graphical ; V < VDS ID= W/LnCox (VGS - VTN)2/2 --- Sat. n Cox W/L =  ID = W/L n Cox {V VDS + VDS2/2}---Triode or Lin Region

  15. CMOS Inverter – Strong pull up & down Rise time Fall Time

  16. INVERTER POWER Supplemental

  17. The Digital CMOS inverter Supplemental

  18. CMOS Logic

  19. CMOS Logic NMOS pull dwn Zbar = AB+CD

  20. CMOS Logic PMOS pull UP Z = A’+B’  C’+D’

  21. CMOS Logic PMOS pull UP Z = A’+B’  C’+D’

  22. CMOS Logic PMOS pull UP Z = A’+B’  C’+D’ Supplemental

  23. CMOS Logic Supplemental

  24. CMOS Logic & Scaling If CL 3 minimum loads or 7.5fF 1/2 um process OR 0.25fF 90nm process tr & tf equal?

  25. CMOS Logic & Scaling > 300X less Pwr

  26. CMOS Logic NMOS pull DWN Z’ = A(D+E) + (BC) PMOS pull UP Z = [A+(D E)]  (B+C) PMOS pull UP Z = A’+B’ + C Supplemental NMOS pull DWN Z’ = ABC

  27. CMOS Analog ID vs. VDS

  28. CMOS Analog ID vs. VDS Early Voltage and Lambda Take Away – effective output resistance Modeled by 1/ID or VA/ID

  29. ID vs. VGS - ID vs. VDS; Amplification

  30. Common Drain in ICs

  31. ID vs. VGS - ID vs. VDS; Amplification

  32. Q pt Bias Stabilization Amplification

  33. Q pt Bias Stabilization Amplification

  34. f1 Bias Considerations Amplification

  35. f2 Considerations Amplification

  36. Common Source Summary • Select Qpt = (VGS, ID, & VDS)and estimate gm and gds =ID/VA • Stabilize the Bias or Quiescent point – VGG =VGSQ + ID RS • RG1, RG2 and RS VGG =VDD RG1/{RG1|| RG2} • Determine Cc1, Cc2, CS • Determine RD after finding gm and gds. • gain = -gm RD||rds||RL mid band gain • Generally – RL >> RD or rds & RG = RG||RG >> Rgen

  37. Common Source Summary``

  38. Why CMOS Inverter NMOS PMOS

  39. Complimentry CMOS & Symbols

  40. Large Signal Equivalent Ckt

  41. Modeling rout Supplemental

  42. Supplemental

  43. Misc. Effects Supplemental

  44. MOSFET DC BIAS

  45. Shifting the Qpt for Gain A Gain A = ΔVDS/ ΔVGS

  46. Distorting the Signal Distortion

  47. Shifting the Qpt con’t Analytical ΔID ΔVGS gm = ΔID/ ΔVGS

  48. MOSFET DC BIAS

  49. MOSFET DC BIAS-CS,CD,CG Gain – modest Rin – High Ro – High Inverting Gain – modest Rin – low Ro – High noninverting Gain –Unity Rin – High Ro – Low Noninverting buffer

  50. Bias Stabilization – Depletion & Enhancement

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