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Technical Report 4 for Pittsburgh Digital Greenhouse

Technical Report 4 for Pittsburgh Digital Greenhouse. High Speed CMOS A/D Converter Circuit for Radio Frequency Signal. Kyusun Choi. Computer Science and Engineering Department The Pennsylvania State University. Project Goals for the Last Quarter.

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Technical Report 4 for Pittsburgh Digital Greenhouse

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  1. Technical Report 4 for Pittsburgh Digital Greenhouse High Speed CMOS A/D Converter Circuit for Radio Frequency Signal Kyusun Choi Computer Science and Engineering Department The Pennsylvania State University

  2. Project Goals for the Last Quarter • Fabricate 2nd prototype chip in 0.18um CMOS • Test 2nd prototype chip • Evaluate the 1st and 2nd chip test results • Present the Final Report

  3. Accomplished Project Milestone • Total 40 chips are received • Each chip contains 10 A/D converters: • - 6 bit ADC with L=1.00um and FAT tree decoder • - 6 bit ADC with L=1.00um and ROM decoder • - 6 bit ADC with L=0.50um and ROM decoder • - 6 bit ADC with L=0.18um and ROM decoder • - 8 bit ADC with L=1.00um and ROM decoder • - 8 bit ADC with L=0.50um and ROM decoder • - 9 bit ADC with L=1.50um and ROM decoder • - 9 bit ADC with L=1.00um and ROM decoder • - 6 bit ADC with L=1.00um, Pipeline, ROM • - 6 bit ADC with L=1.00um, S&H, ROM

  4. Accomplished Project Milestone • 2nd prototype chips (0.18um) are working • Test results for the 10 ADCs:

  5. 2nd prototype chip summary • Die size: 2.64*2.64 mm2 (total) • 1.88*1.88 mm2 (core) • 0.18um Digital Logic CMOS • 56,069 transistors • 84 pins (18 pins for power)

  6. Chip Test Results (1) • 6bit 1.00 um with Fat Tree ADC • 100 KHz Saw wave

  7. Chip Test Results (2) • 6bit 1.00 um with ROM ADC • 100 KHz Saw wave

  8. Chip Test Results (3) • Delay of pad and multiplexor • Tin to Tout

  9. Chip Test Results (4) • ADC signal operation (0.0V to 1.8V) • Actual measurement(6bit 1.00 um ROM)

  10. Chip Test Results (5) • ADC signal operation (0.0V to 1.8V) • Actual measurement(6bit 1.00 um Fat Tree)

  11. Chip Test Results (6) • ADC signal operation (0.0V to 1.8V) • Simulation with T1AX_LO_EPI (nSec)

  12. Chip Test Results (7) • ADC signal operation (0.0V to 1.8V) • Simulation with TSMC_TT (nSec)

  13. Chip Test Results (8) • ADC signal operation (0.5V to 1.1V) • Simulation with T1AX_LO_EPI (nSec)

  14. Chip Test Results (9) • ADC signal operation (0.5V to 1.1V) • Simulation with TSMC_TT (nSec)

  15. Chip Test Results (10) • DNL and INL measurement • 6bit 1.00 um • DNL = 0.36 LSB INL = 1.36 LSB

  16. Chip Test Results (11) • Sampling rates & Power consumption • Actual measurement

  17. Chip Test Results (12) • Sampling rates & Power consumption • Simulation results with TSMC_TT

  18. Chip Test Results (13) • FFT with original 1MHz sine wave input • fsample = 200 MHz • 6bit 1.00 um (0.25 um) • SNR = 37.78 dB • SNDR = 36.56 dB • SFDR = 37.86 dB • ENOB = 5.78 bits

  19. Chip Test Results (14) • FFT with ADC output of 1MHz sine wave input • fsample = 200 MHz • 6bit 1.00 um (0.25 um) • SNR = 43.85 dB • SNDR = 33.17 dB • SFDR = 37.93 dB • ENOB = 5.22 bits

  20. Chip Test Results (15) • FFT with ADC output of 80KHz sine wave input • fsample = 10 MHz • 6bit 1.00 um (0.18um) • SNR = 23.40 dB • SNDR = 21.83 dB • SFDR = 9.13 dB • ENOB = 3.33 bits

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