1 / 15

Lecture 8 Shelving in Superscalar Processors (Part 1)

Learn about shelving in advanced computer architecture, design space, layout, and implementation of shelving buffers. Explore operand fetch policies and efficient buffer utilization.

ypayton
Download Presentation

Lecture 8 Shelving in Superscalar Processors (Part 1)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Lecture 8Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

  2. Direct Issue

  3. The principle of shelving: Indirect Issue

  4. Design Space of Shelving

  5. Scope of Shelving

  6. Layout of Shelving Buffers

  7. Implementation of Shelving Buffer

  8. Basic Variants of Shelving Buffers

  9. Using a Combined Buffer for Shelving, Renaming, and Reordering

  10. Number of Shelving Buffer Entries

  11. Number of read and write ports • how many instructions may be written into (input ports) or • read out from (output parts) a particular shelving buffer in a cycle • depend on individual, group, or central reservation stations

  12. Shelving: Operand Fetch Policy

  13. Operand Fetch Policies

  14. Operand fetch during instruction issue Reg. file

  15. Operand fetch during instruction dispatch Reg. file

More Related