Physical Design of FabScalar Generated Superscalar Processors

1. Physical Design of FabScalar Generated Superscalar Processors EE6052 Class Project Wei Zhang

2. Outline • Heterogeneous Multi-Core Processors • FabScalar • Physical design of FabScalar generated cores • Things we can do • Conclusion Wei

3. Heterogeneous Multi-Core Processors Heterogeneous multi-Core processor • Contains multiple, differently-designed superscalar core types that can streamline the execution of diverse programs. • The core types differ from each other and target at different applications. Superscalar processor • Utilizes instruction level parallelism. Executes more than one instruction during a clock-cycle. • Dispatch instructions to redundant functional units such as ALU, multiplier, bit shifter, etc on the processor. “Achilles’ heel” of heterogeneous multi-core processor design • Design and verification effort is multiplied by the number of different core types, which limits the amount of architectural diversity that can be practically implemented. Wei

4. FabScalar • A toolset developed to automatically compose RTL designs of arbitrary cores within a canonical superscalar template. • Frames superscalar processors in a canonical template which defines canonical pipeline stages and interfaces among them. • A Canonical Pipeline Stage Library (CPSL) provides many implementations of each canonical pipeline stage that differs in their superscalar dimensions. • An RTL generation tool uses the template and CPSL to automatically generate an overall core of desired configuration. Wei

5. Canonical Pipeline Stages • The pipeline stages and interfaces are the same for all the superscalar processors. • Each pipeline stage is composed from the Canonical Pipeline Stage Library. Wei

6. Canonical Pipeline Stage Library Wei

7. FabMem: A Multiported RAM and CAM Compiler • Estimates read/write delays, read/write energies, and areas of user-specified multi-ported RAMs/CAMs. • Generates layouts of desired RAMs/CAMs. Limitations • FabMem is tied to a specific technology (FreePDK45). • The largest supported RAM is 512 words. • FabMem can generate RAMs for only 2XR-XW and XR-XW configurations. The maximum number of read ports is 16. The maximum number of write ports is 8. • The degree of column muxing in RAMs is limited to 1, 2, and 4. • The largest supported CAM is 256 words. • FabMem can generate CAMs for only XR-XW configurations. The maximum number of read ports is 8. The maximum number of write ports is 8. Wei

8. Physical Design – by FabScalar Group • Use FabMem to generate custom designs of critical memory structures. • Course-grained floorplanning. • Little consideration of power, area and performance issues. • Use FreePDK45, a 45nm based standard cell library, for logic synthesis and place-and-route. Wei

9. Physical Design – Things We Can Do • Floorplanning • Data path design • Memory design – comparison between FabMem and other memory compilers • Cadence vs Synopsys • Power planning Wei

10. Conclusion • Heterogeneous Multi-Core Processors have many advantages • FabScalar uses canonical pipeline stages for superscalar processor generation. • Physical design of FabScalar generated cores remains to be further investigated. Wei