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Arithmetic for Computers

Arithmetic for Computers. Chapter 3 Sections 3.1 – 3.5 & 3.8 Appendix C.1 – C.3, C.5 – C.6 Dr. Iyad F. Jafar. Outline. Addition and Subtraction Overflow Detection Faster Addition The 1-Bit ALU The 32-bit MIPS ALU Shift Operations Multiplication Division

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Arithmetic for Computers

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  1. Arithmetic for Computers Chapter 3 Sections 3.1 – 3.5 & 3.8 Appendix C.1 – C.3, C.5 – C.6 Dr. Iyad F. Jafar

  2. Outline • Addition and Subtraction • Overflow Detection • Faster Addition • The 1-Bit ALU • The 32-bit MIPS ALU • Shift Operations • Multiplication • Division • Floating Point Numbers • Fallacies and Pitfalls

  3. 4 + 3 7 0100 0011 0111 -4 - (-3) 1100 1101 4 - 3 1 0100 1101 1 0001 -4 + 3 -1 -4 + 3 -1 1100 0011 1111 1100 0011 1111 Addition and Subtraction • Add corresponding bits including the sign bit and ignore the carry out of the MSB • For subtraction, add the negative

  4. Cin Cin Cin Cin Cin Cin Cout Cout Cout Cout Cout Cout 1 0 1 0 1 0 1 1 1 0 0 0 0+ 0 0+ 0 1+ 1 1+ 1 1+ 0 1+ 0 Cin Overflow Cout Detecting Overflow • When do we get overflow? • Adding two positive numbers and get a negative number • When we add two negative numbers and get a positive number • Investigate the sign bit! + + - - - - + + - - + + + - + - - + 0 1 0 1 1 0 No overflow Overflow Overflow No Overflow No Overflow No Overflow Overflow when carry into sign bit does not equal thecarry out

  5. CarryIn A1 Sum + B1 CarryOut Cout A A Sum AB AB 00 01 11 10 00 01 11 10 Cin Cin 0 0 1 1 B B Addition and Subtraction • How to perform addition in hardware? • Design 32-bit adder (two 32-bit inputs !!!!) • Cell design ! • 1-bit Full Adder A B CinCoutSum 0 0 0 00 0 0 1 01 0 1 0 01 0 1 1 10 1 0 0 01 1 0 1 10 1 1 0 10 1 1 1 11 0 1 0 1 0 0 1 0 1 0 1 0 0 1 1 1 +BCin +ACin Cout = AB Sum =A Å B ÅCin

  6. Addition and Subtraction • 32-bit ripple-carry adder • Cascade 32 copies and wire them up through the Cin and Cout • How long does it take to get the result ? A31 B31 A2 A1 B1 A0 B0 B2 FA FA FA FA 0 C32 S31 S2 S1 S0

  7. Addition and Subtraction • 32-bit ripple-carry Subtractor • Subtraction is addition of the negative! • Compute the 2s complement = 1s complement + 1 B1 B31 B2 B0 A31 A2 A1 A0 FA FA FA FA 1 B32 D31 D2 D1 D0

  8. Addition and Subtraction • 32-bit ripple-carry adder/subtractor • Redundancy in hardware!! Subtraction is addition of the negative! • Use one adder and configure the second input • Remember X Å 1 = X’ and X Å 0 = X Add/Sub 0  ADD 1  Subtract B31 B1 B0 B2 A31 A2 A1 A0 FA FA FA FA C32 S31 S2 S1 S0

  9. Faster Addition • The ripple-carry adder is slow! • We have to wait until the carry is propagated to the final position in order to read out the addition or subtraction result. • Carry generation is associated with two levels of gates at each bit position Coi = AiBi + AiCini + BiCini • Total delay = gate delay x 2 x number of bits • Example • 16 bit adder  delay is 32 delay units • Can we go faster? • What if we generate the carries in parallel?

  10. Faster Addition • The carries can be expressed by the Adders inputs and c0 exclusively! • Add a separate hardware to compute the carry in parallel! • Carry-lookahead Adder A31 – A0 c4 B31 – B0 c3 c2 c1 c0

  11. Faster Addition • In a 4-bit adder, the equations of the carries are c1 = (b0 . c0) + (a0 . c0) + (a0 . b0) c2 = (b1 . c1) + (a1 . c1) + (a1 . b1) c3 = (b2 . c2) + (a2 . c2) + (a2 . b2) c4 = (b3 . c3) + (a3 . c3) + (a3 . b3) • By substitution c2 = (a1 . a0 . b0) + (a1 . a0 . c0) + (a1 . b0 . c0) + (b1 . a0 . b0) + (b1 . a0 . c0 ) + (b1 . b0 . c0) + (a1 . b1) c3 = (b2 . a1 . a0 . b0) + (b2 . a1 . a0 . c0) + (b2 . a1 . b0 . c0) + (b2 . b1 . a0 . b0) + (b2 . b1 . a0 . c0 ) + (b2 . b1 . b0 . c0) + (b2 . a1 . b1) + (a2 . a1 . a0 . b0) + (a2 . a1 . a0 . c0) + (a2 . a1 . b0 . c0) + (a2 . b1 . a0 . b0)+ (a2 . b1 . a0 . c0 ) + (a2 . b1 . b0 . c0) + (a2 . a1 . b1) + (a2 . b2) c4 = …… • All carries require two gate delays ! • However, imagine the equation/cost if the adder is 32 bits ??

  12. Faster Addition • We can reduce the logic cost by simple simplification • ci+1 = (ai . bi) + (bi . ci) + (ai . ci) = (ai. bi) + (ai + bi). ci = gi + pi . ci • gi : carry generate • pi : carry propagate • Carry equations for 4 bit adder • c1 = g0 + p0 . c0 • c2 = g1 + p1. c1 = g1 + (p1 . g0) + (p1 . p0 . c0) • c3 = g2 + p2. c2 = g2 + (p2 . g1) + (p2 . p1 . g0) + (p2 . p1 . p0 . c0) • c4 = g3 + p3. c3= g3 + (p3 . g2) + (p3 . p2 . g1) + (p3 . p2 . p1 . g0) + (p3 . p2 . p1 . p0 . c0) • Delay to generate c4 is 3 gate delay • Still cost is high for large adders ! ! !

  13. Faster Addition • 2nd Level of Abstraction • Example: 16-bit adder. assume that we have four 4-bit carry-lookahead adders • These 4-bit adders will be designed to produce supper generate (G) and propagate (P) signals • P  the four bits propagate a carry to the next four bits • G  the four bits generate a carry to the next four bits • The super carry signals are fed to a separate carry generation unit A3-A0 B3-B0 4-bit CLA c0 P0 S3-S0 G0

  14. Faster Addition • Need to generate the carry propagate and generate signals at higher level • Think of each 4-bit adder block as a single unit that can either generate or propagate a carry. A3-A0 B3-B0 A15-A12 B15-B12 A11-A8 B11-B8 A7-A4 B7-B4 4-bit CLA 4-bit CLA 4-bit CLA 4-bit CLA C0 S15-S12 S11-S8 S7-S4 S3-S0 Carry Generation Unit G3 P3 C3 G2 P2 C2 G1 P1 C1 G0 P0 C4

  15. Faster Addition • Super propagate signals • P0 = p3⋅p2⋅p1⋅p0 (how can the first 4-bit adder propagate c0?) • P1 = p7⋅p6⋅p5⋅p4 • P2 = p11⋅p10⋅p9⋅p8 • P3 = p15⋅p14⋅p13⋅p12 • Super generate signals • G0 = g3+(p3 ⋅ g2)+(p3⋅p2⋅g1)+(p3⋅p2⋅p1⋅g0) • G1 = g7+(p7 ⋅ g6)+(p7⋅p6⋅g5)+(p7⋅p6⋅p5⋅g4) • G2 = g11+(p11 ⋅ g10)+(p11⋅p10⋅g9)+(p11⋅p10⋅p9⋅g8) • G3 = g15+(p15 ⋅ g14)+(p15⋅p14⋅g13)+(p15⋅p14⋅p13⋅g12) • Carry signal at higher levels are • C1 = G0 + (P0 ⋅ c0) • C2 = G1 + (P1 ⋅ G0) + (P1⋅P0⋅c0) • C3 = G2 + (P2 ⋅ G1) + (P2⋅P1⋅G0) + (P2⋅P1⋅P0⋅c0) • C4 = G3 + (P3 ⋅ G2) + (P3⋅P2⋅G1) + (P3⋅P2⋅P1⋅G0) + (P3⋅P2⋅P1⋅P0⋅c0)

  16. Faster Addition • Each supper carry signal is two level implementation in terms of Pi and Gi • Pi is one level of gates while Gi is two and expressed in terms of pi and gi • pi and giare one level of gates • Total delay is 2 + 2 + 1 = 5 • 16-bit CLA is ~6 times faster than the 16-bit ripple carry adder

  17. zero ovf 1 1 A 32 ALU result 32 B 32 4 m (operation) Designing the ALU • We want to design an ALU that • Supports logic operations • Supports arithmetic operations • Supports the set-on-less-than instruction • Supports test for equality • With special handling to • sign extension • zero extension • overflow detection

  18. 0 1 Designing the ALU • We start by 1-bit ALU • Starting with logical operations is easier since they map directly to hardware Two operands, two results.We need only one result... Use 2-to MUX Operation AB A B Result A+B The Operation input comes from logic that looks at the opcode

  19. Operation A 0 0 Result 1 1 + 2 B Designing the ALU • How about addition? Add an Adder Cin Connect Cin(from previous bit) and Cout(to next bit) Expand Mux to 3-to-1 (Op is now 2 bits) Cout

  20. Operation A 0 1 Result 0 + 2 1 Cout Designing the ALU Use the same adder for subtraction • How about subtraction? Cin BInvert Depending operation, choose whether to compute the 2s complement of B or not (MUX or XOR) B For 2s complement, define the Binvert signal and set Cin of LSB to 1

  21. Operation A 0 1 Result 0 0 + 2 1 1 Cout Designing the ALU AInvert • Can we add the NOR instruction? BInvert Cin No need to add a NOR gate !! Use Demorgan’s theorem, an inverter and 2-to-1 MUX B Define the Ainvert signal

  22. Operation A 0 1 Result 0 0 + 2 1 1 Cout Designing the ALU • Building the 32-bit ALU • Simply, we need to wire up 32 copies of the ALU we designed earlier with special care to the LSB ALU • The Cin and Binvert signals are the same, tie them together into one signal BNegate AInvert BNegate B LSB ALU

  23. A0 Cin B0 Result0 ALU0 Cout A1 Cin B1 Result1 ALU1 Cout A2 Cin B2 Result2 ALU2 Cout A31 Result31 Cin B31 ALU31 Cout Designing the ALU • Building the 32-bit ALU BNegate Operation Note that the Cin and Bnegate for the LSB are the same in order to compute the 2s complement in case of subtraction Cout

  24. Designing the ALU • Supporting SLT instruction • Expand the multiplexer for one more input (Less). • Subtract the two registers and feed the sign bit (the result of bit 31) back to the Less input of the LSB ALU • The Less inputs of remaining ALUs is 0.

  25. A0 Cin B0 Result0 ALU0 Less Cout A1 Cin B1 Result1 ALU1 0 Less Cout A2 Cin B2 Result2 ALU2 0 0 Less Cout A31 Result31 Cin B31 ALU31 Less Cout Designing the ALU BNegate Operation • The second version of 32-bit ALU • For SLT instruction, the MSB is fed back to the LSB while other bits are set to zero! • The operation is basically subtraction OverFlow Set Cout

  26. Designing the ALU • Supporting Branch instructions • Basically, subtract two registers! • However, we need to generate a signal that indicates whether the result is zero or not. • Simply OR the result bits and take the complement. • This signal will be used to make the selection between the branch address and the PC. • Example on using the Zero signal to select the address for BEQ instruction

  27. A0 Cin B0 Result0 ALU0 Less Cout A1 Cin B1 Result1 ALU1 0 Less Cout A2 Cin B2 Result2 ALU2 0 Less Cout A31 Result31 Cin B31 ALU31 0 Less Cout Designing the ALU BNegate Operation The 32-bit ALU OverFlow Set Cout

  28. Designing the ALU • The 32-bit ALU List of Supported Operations

  29. Shift Operations • Shift operations are commonly needed! • MIPS ISA specifies three shift instructions • Two logical shift instructions SLL $rt, $rs, shift_amount#R[rt] = R[rs] << shift_amount SRL $rt, $rs, shift_amount#R[rt] = R[rs] >> shift_amount • One arithmetic shift instruction SRA $rt, $rs, shift_amount#R[rt] = R[rs] >> shift_amount • What is the difference? • Unlike the SRL, the SRA instruction preserves the sign of the number! • Encoding op rs rt rd shamt funct R-type 6 5 5 5 5 6

  30. 0010 0011 0111 0110 1010 1111 0000 1101 $t1 0000 0000 0010 0011 0111 0110 1010 1111 $t1 $t1 0000 0000 0000 0000 0000 0000 1010 1111 0000 0000 0000 0000 0000 0000 0000 0101 $t3 0000 0000 0000 0000 0000 0000 0010 1000 $t3 Shift Operations 1. You need to extract the 2nd byte of a 4-byte word in $t1 • Example 1. 8 srl $t1, $t1, 8 0000 0000 0000 00000000 0000 1111 1111 andi $t1, $t1, 0x00FF 2. You want to multiply $t3 by 8 (note: 8 equals 23) (equals 5) sll $t3, $t3, 3 # move 3 places to the left (equals 40)

  31. Shift Operations • How are these instructions implemented? • Outside the ALU • Shift registers  slow; shifting by one bit requires one cycle! • Barrel Shifters • A digital circuit that can shift a data word by a specified number of bits in one clock cycle, if long enough! • Simply a set of multiplexors !

  32. Shift Operations D0 D3 D2 D1 Y0 • Example 2. 4-bit barrel shifter (rotate to left by 0, 1, 2, or 3 bits) D1 D0 D3 D2 Y1 4-bit Barrel Shifter D Y 4 4 D2 D1 D0 D3 Y2 S0 S1 D3 D2 D1 D0 Y3

  33. Multiplication Multiplicand 4 2 1 Multiplying two 3-digit numbers A and B Multiplier x 1 2 3 1 2 6 3 n partial products, where B is n digits long 8 4 2 + 4 2 1 n - 1 additions 5 1 7 8 3 In Binary... 6 x 5 1 1 0 Each partial product is either: 110 (A*1) or 000 (A*0) x 1 0 1 1 1 0 0 0 0 + 1 1 0 Equals 30 Note: Product may take as manyas two times the number of bits! 1 1 1 1 0

  34. Multiplication • Multiplication Steps Step1: LSB of multiplier is 1 Add a copy of multiplicand 1 1 0 0 1 1 0 1 1 0 0 0 Step2: Shift multiplier right to reveal new LSB Shift multiplicand left to multiply by 2 x 1 0 1 0 1 1 1 1 0 Step 3: LSB of multiplier is 0 Add zero 0 0 0 0 1 1 0 0 0 + Step 4: Shift multiplier right, multiplicand left Step 5: LSB of multiplier is 1  Add a copy of multiplicand 0 0 1 1 0 1 1 1 1 0 Step 6: Add partial products Done! Thus, we need hardware to: 1. Hold multiplier (32 bits) and shift it right 2. Hold multiplicand (32 bits) and shift it left (requires 64 bits) 3. Hold product (result) (64 bits) 4. Add the multiplicand to the current result

  35. Shift Left Multiplicand 64 bit Multiplier 64-bit Shift Right 32 bit Write Product 64 bit Multiplication 1. Hold multiplier (32 bits) and shift it right • Multiplication Hardware 2. Hold multiplicand (32 bits) and shift it left (requires 64 bits) 3. Hold product (result) (64 bits) 4. Add the multiplicand to the current result 5. Control the whole process LSB Control

  36. xxxx1101 ShLeft 8 bit ShRight 0101 4 bit 8-bit Control 000000000 Write 8 bit Multiplication MultiplicandMultiplierProduct xxxx1101010100000000 • Example 3. (4-bit multiplication) Initial Values • 1-->Add Multiplicand to Product • Shift M’cand left, M’plier right + xxx11010001000001101 • 0-->Do nothing • Shift M’cand left, M’plier right xx110100000100001101 + x1101000000001000001 • 1-->Add Multiplicand to Product • Shift M’cand left, M’plier right 11010000000001000001 • 0-->Do nothing • Shift M’cand left, M’plier right

  37. Shift Right Multiplicand Multiplier 32 bit Control 32 bit Write 32-bit Shift Right LH Product RH Product 64 bit Multiplication • A Cheaper Implementation • Even though we’re only adding 32 bits at a time, we need a 64-bit adder • Instead, hold the multiplicand still and shift the product register right! • Now we’re only adding 32 bits each time Extra bit for carryout

  38. Multiplicand 32 bit Control Write 32-bit Shift Right LH Product Multiplier 64 bit Multiplication • A Cheaper than the Cheaper Implementation • Note that we’re shifting bits out of the multiplier and into the product • Why not put these together into the same register?!! • As space opens up in the multiplier, overwrite it with the product bits LSB

  39. Multiplication • Fast Multiplication • Use 31 32-bit adders to compute the partial products • One input is the multiplicandANDedwith a multiplier, and the other is the partial product from previous step. • Question? Show the multiplication tree to compute 5 X 3. Assume unsigned numbers represented using 3 bits and we have 4-bit ALU.

  40. Multiplication • MIPS Multiplication • Two multiplication instructions mult $s0, $s1 # hi||lo = $s0 * $s1 multu $s0, $s1 # hi||lo = $s0 * $s1 • The result is 64 bits and it stored in two special registers • LO  holds the lower 32 bits of the result • Hi  holds the upper 32 bits of the result • The contents of these registers can be read using two special instructions op rs rt rd shamt funct R-type 6 5 5 5 5 6 mfhi $t5 # move Hi to register $t5 mflo $t6 # move Lo to register $t6

  41. Multiplication • MIPS Multiplication (NOTES) • Both multiplication instructions ignore overflow! • It is the responsibility of the software to check if the result fits into 32 bits ! • For MULTU, there is no overflow if hi is 0 • For MULT, there is no overflow if hi is the replicated sign of lo • Question! • Modify the designed multiplier to support signed multiplication.

  42. -45 -000 -30 -101 -30 -101 -15 -101 -000 Division Dividend = Divisor * Quotient + Remainder 14 5 0 1 1 1 0 quotient divisor 101 1001001 3 2 2 1 73 15 48323 100 1 dividend 3 3 100 0 3 2 11 0 2 3 1 1 remainder 3 8 11 Idea: Repeatedly subtract divisor. Shift as appropriate.

  43. -000 -101 -101 -101 -000 Division Looking at the alignment a little differently… 0 1 1 1 0 0 1 1 1 0 0101 01001001 101 1001001 Make the dividend 8 bits and the divisor 4 bits by filling in with 0’s -01010000 01001001 100 1 -00101000 Each iteration, re-express the entire remainder as 8 bits Note: At any step, the dividend = divisor * quotient + current remainder 00100001 100 0 -00010100 00001101 11 0 -00001010 00000011 Try subtracting the divisor from the current remainder each time – if it doesn’t fit, restore the remainder 1 1 -00000101 00000011 11

  44. Shift Right Divisor 64 bit if (remainder< 0) { Quotient remainder+=divisor;left shift quotient 1, LSB=0 32 bit 64-bit Shift Left } else { left shift quotient 1, LSB=1 Write Control } Remainder 64 bit Division Division Hardware 1. Hold divisor (32 bits) and shift it right (requires 64 bits) 2. Hold remainder (64 bits) 3. Hold quotient (result) (32 bits) and shift it left 4. Subtract the divisor from the current result 5. Control the whole process Algorithm initialize registers (divisor in LHS); for (i=0; i<33; i++) { remainder -= divisor;

  45. Division • Read pages 236 -242

  46. Division • MIPS Division • Two multiplication instructions div $s0, $s1 divu $s0, $s1 • As with multiply, divide ignores overflow so software must determine if the quotient is too large. • Software must also check the divisor to avoid division by 0 • Signed division • Remember the signs of the dividend and divisor and use to determine the sign of the quotient • The sign of the remainder is always the same as the dividend (Check by yourself the division of 5/2 using different combinations of the signs of the dividend and the divisor) # hi = $s0 / $s1 # lo = $s0 mod $s1 op rs rt rd shamt funct R-type 6 5 5 5 5 6

  47. Floating Point Numbers • Numbers used so far are 32-bit integers! • How about larger and smaller values? How about fractions? • 4,600,000,000 or 4.6 x 109 • 0.0000000000000000000000000166 or 1.6 x 10-27 • 3.5 , - 0.0213 • The IEEE 754 FP Standard ! • Uses 32 (single precision) or 64 bits (double precision) to represent numbers • Any number is represented by 3 parts: sign, significand, and exponent • Used in most computers

  48. Floating Point Numbers • The IEEE 754 FP Standard • Single precision (32 bits) • Normalized representation (no leading zeros and one none zero bit to the left of binary point in the significand) • Since the bit to the left of the binary point is always 1, it is implied and not stored in the fraction (WHY!) Value = (-1)sign x (Fraction+1) x 2Exponent • Smallest number is 1.175494350822288e-038 • Largest number is 3.402823466385289e+038

  49. Floating Point Numbers • The IEEE 754 FP Standard • Double precision (64 bits) • Normalized representation (no leading zeros and one none zero bit to the left of binary point in the significand) • Since the bit to the left of the binary point is always 1, it is implied and not stored in the fraction (WHY!) Value = (-1)sign x (Fraction+1) x 2Exponent • Smallest number is 2.225073858507201e-308 • Largest number is 1.797693134862316e+308

  50. Floating Point Numbers • The IEEE 754 FP Standard ! • The way numbers are represented simplifies sorting of floating numbers using integer comparison • The fraction is sign-magnitude • The exponent is signed 2s complement • Placing the exponent before the significand • The exponent is biased • A constant value is added to represent all exponents with positive numbers • In single precision, bias is 127 • Exponent -3 is represented as -3 + 127 = 124 • Exponent 5 is represented as 5 + 127 = 132 • While in double precision , the bias is 1023 • So in biased notation Value = (-1)sign x (Fraction+1) x 2Exponent - Bias

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