Design Verification

1. Design Verification Class Presentation of Course : ASIC CMOS System Design Presented By: Majid Nabi

2. Outline Introduction Simulation Based Verification Formal Verification Assertion Based Verification New Methodologies in Verification Conclusion References Design Verification

3. Introduction • Functional errors in RTL are • not eliminated by synthesis • not discovered by equivalence checking • Where do bugs come from? • Incorrect specifications • Misinterpretation of specifications • Misunderstandings between designers • Missed cases • Protocol non-conformance • Resource conflicts • Cycle-level timing errors Design Verification

4. Introduction • Verification requires something to check • Properties can be represented in many ways • Checkers in HDL or other language • Temporal logic • Properties can be specified at various points: • End-to-End (black-box) properties • Internal properties (white-box) • “Coverage”is the key concept Maximize the probability of stimulating and detecting bugs, at minimum cost Design Verification

5. Introduction • Verification Methods: • Simulation Based Verification • Formal Verification (FV) • Assertion Based verification (ABV) Reconvergent path Model [1] (Redundancy is used to guard against misinterpretation) Design Verification

6. Outline Introduction Simulation Based Verification Formal Verification Assertion Based Verification New Methodologies in Verification Conclusion References Design Verification

7. Simulation Based Verification • Dynamic Verification • Need test vector and a simulation engine • Test vector generation • Random • Constrained Random • Directed Design Verification

8. Simulation Based Verification Measures the percentage of code executed by the test.` Coverage Metrics • Different coverage metrics: • Code-based. • Circuit structure-based. • Functionality-based. • etc. • Statement Coverage • Path Coverage • Expression Coverage • Toggle Coverage • … • High coverage indicates that fewer bugs remained Measures the percentage of gates visited during the test. Measures the percentage of functionality checked by the test. Design Verification

9. Outline Introduction Simulation Based Verification Formal Verification Assertion Based Verification New Methodologies in Verification Conclusion References Design Verification

10. Formal Verification • Static Verification • Compression between a mathematical model of design and design properties • No need test vector but need design Property Theorem Proving Equivalence Checking Formal Verification Decision Diagram Model Checking Design Verification

11. Formal Verification • Equivalence Checking • It compares two netlists • It can detect bugs in the synthesis software Equivalence Checking [1] Design Verification

12. Model Checking • Derive a model of a system using the transition system formalism : TS • Capture interesting properties of the system with using a temporal logic :  • Verify that the system has the required property via model checking : TS  • If the property does not hold a counter-example will be generated, Formal Verification Design Verification

13. Syntax Semantic Intuition F ::= P …primitive propositions | !F | F && F | F || F | F -> F…propositional connectives | AG F | EG F | AF F | EF F…temporal operators | AX F | EX F | A[F U F] | E[F U F] path quantifier AG p tempora modality …along All paths p holds Globally EG p …there Exists a path where p holds Globally AF p …along All paths p holds at some state in the Future EF p …there Exists a path where p holds at some state in the Future Formal Verification Computational Tree Logic (CTL) Design Verification

14. Formal Verification • Model Checking Properties Intermediate Format Model Checking (MC) Engine Y/N BDD Design (HDL) Intermediate Format DFG Design Verification

15. Formal Verification • Coverage In Formal Verification • In model-checking we may visit all states. Does it mean that coverage is always 100% ? • In Model-checking, Coverage metrics determine the completeness of given properties Design Verification

16. Outline Introduction Simulation Based Verification Formal Verification Assertion Based Verification New Methodologies in Verification Conclusion References Design Verification

17. Assertion Based Verification • An Assertion is a statement about a design’s intended behavior ,which must be verified • Benefits of Assertions: • Improving Observability • Reducing Debug Time • Improving integration through correct usage checking • A design team inserts boundary assertions to monitor correct interface communication during integration verification • Improving verification efficiency • Find bugs faster • Work at all times • Work with all tools • Facilitate formal analysis • Improving communication through documentation Design Verification

18. Assertion Based Verification Assertions have been used by many prominent companies [2]: • 34% of all bugs on DEC Alpha21164 project • 17% of all bugs on Cyrix M3(p1) project • 25% of all bugs on DEC alpha21264 • 25% of all bugs on Cyrix M3(p2) • 85% of all bugs using OVL assertions on HP Design Verification

19. . With assertions 302 . 260 . 265 Without Assertions . . . 180 Bugs Found . . . . 50,000 CPU hours 200,000 CPU hours simulation timeline Assertion Based Verification • 4300 OVL assertion monitors added to a 10M gate ASIC • Reach stable model quicker than previous method • Bug report open rate increased between projects • Bug report close rate decreased between projects • 85% of bugs in simulation found using assertions • Turn random on sooner Results in HP[2] Design Verification

20. Assertion Based Verification Available Assertions: • OVL Assertions (Open Verification Library) • PSL (Property Specification Language) • System Verilog Assertions Design Verification

21. Assertion Based Verification Assertion Monitor Library assert_never underflow ( clk, reset_n, (q_valid==1’b1) && (q_underflow==1’b1)); moduleassert_never (clk, reset_ input clk, reset_n, test_expr; parameter severity_level = 0; parameter msg="ASSERT NEVER VIOLATION"; // ASSERT: PRAGMA HERE //synopsys translate_off `ifdef ASSERT_ON integer error_count; initial error_count = 0; always @(posedge clk) begin `ifdef ASSERT_GLOBAL_RESET if (`ASSERT_GLOBAL_RESET != 1'b0) begin `else if (reset_n != 0) begin// active low reset_n `endif if (test_expr == 1'b1) begin error_count = error_count + 1; `ifdef ASSERT_MAX_REPORT_ERROR if (error_count<=`ASSERT_MAX_REPORT_ERROR) `endif $display("%s : severity %0d : time %0t : %m", msg, severity_level, $time); if (severity_level == 0) $finish; end end end `endif //synopsys translate_on endmodule RTL Design Design Verification

22. width min start_event` max 0 check_event time Assertion Based Verification ASSERT_FRAME SYNOPSISassert_frame#(severity_level, min, max) inst ( ck, start_event, check_expr); req ack assert_frame#(0, 3, 7) req_ack ( ck, req, ack); Design Verification

23. Assertion Based Verification module fifo (clk, fifo_clr_n, fifo_reset_n, push, pop, data_in, data_out); parameter fifo_width = `FIFO_WIDTH; parameter fifo_depth = `FIFO_DEPTH; parameter fifo_cntr_w = `FIFO_CNTR_W; input clk, fifo_clr_n, fifo_reset_n, push, pop; input [fifo_width-1:0] data_in; output [fifo_width-1:0] data_out; wire [fifo_width-1:0] data_out; reg [fifo_width-1:0] fifo[fifo_depth-1:0]; reg [fifo_cntr_w-1:0] cnt; // count items in FIFO . . . // RTL FIFO Code Here . . . ‘ifdef ASSERT_ON // OVL Assert that the FIFO cannot overflow assert_never no_overflow (clk,(fifo_reset_n & fifo_clr_n), ({push,pop}==2'b10 && cnt==fifo_depth)); // OVL Assert that the FIFO cannot underflow assert_never no_underflow (clk,(fifo_reset_n & fifo_clr_n), ({push,pop}==2'b01 && cnt==0)); ‘endif endmodule Design Verification

24. Outline Introduction Simulation Based Verification Formal Verification Assertion Based Verification New Methodologies in Verification Conclusion References Design Verification

25. New Methodologies in Verification[7] • Design complexity means that verification teams must be able to produce more tests with less redundancy to cover targeted features more quickly • advanced verification technologies and methodologies: • Assertion-based verification • Constrained random tests • Functional coverage • Testbench automation • The most important languages to emerge for advanced design and verification are SystemVerilog and SystemC Design Verification

26. New Methodologies in Verification[7] SystemVerilog • Promotes advanced functional verification constructs that automate the detection of bugs and the thorough coverage of designs • Improves modeling for better visibility and fewer bugs • Improves the testbench infrastructure by supporting constrained random testing, automation, assertions, coverage, and testbench reuse SystemC • Enables engineers to capture designs at higher levels of abstraction • Perform verification using high-level test strategies that may include software • Because SystemC is an extension of C++, it has a number of inherent properties such as classes, templates, and multiple inheritance that lend themselves to building reusable transaction-level components for functional verification. Design Verification

27. New Methodologies in Verification • TBV : Transactor based Verification [3] • Moving from transaction level to RTL requires to redefine TLM testbenches and assertions • Such a wasteful and error prone conversion can be avoided by adopting transactor-based verification (TBV) • mixing TLM and RTL components • reusing TLM assertions and testbenches at RTL • [3] theoretically compares the quality of the TBV towards the rewriting of assertions and testbenches at RTL with respect to both fault coverage and assertion coverage Design Verification

28. Outline Introduction Simulation Based Verification Formal Verification Assertion Based Verification New Methodologies in Verification Conclusion References Design Verification

29. Conclusion • Verification method and source of bugs in design • Simulation based verification, Formal verification and assertion based verification have been described • Benefits of Assertion based verification and some results • Coverage is the key concept in every verification methodology • Transaction level of verification • Mixing TLM and RTL design and verification plan Design Verification

30. Outline Introduction Simulation Based Verification Formal Verification Assertion Based Verification New Methodologies in Verification Conclusion References Design Verification

31. References • Janick jergeron,“.Writing Testbench, Functional Verification of HDL Models” , Kluwer.Academic Publisher • HarryD.Foster,Adam C.Krolnik,David J.Lacey,”Assertion-Based Design”,2nd edition, Kluwer.Academic Publisher,2004 • Nicola Bombieri,Franco Fummi,Graziano Pravadelli,” On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL”, Dipartimento di Informatica - Universit`a diVerona,DATE06 • Ali Habibi, Sofi`ene Tahar, Amer Samarah, Donglin Li and O. Ait Mohamed,”Efficient Assertion Based Verification using TLM”,DATE06 • Felice Balarin, Roberto Passerone,“Functional Verication Methodology Based on Formal Interface Specication and Transactor Generation”,DATE06 • Daniel Karlsson, Petru Eles, Zebo Peng,”Formal Verification of SystemC Designs Using a Petri-Net Based Representation”,DATE06 • Mentor Graphics Corp,”Transaction-Level Modeling and Advanced Verification Come Together with SystemC and SystemVerilog”,March 2006 • Mentor Graphics Corp ,”Mentor Graphics Unveils Next Generation of Functional Verification”,May 2006 Design Verification