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Improvement of ECG processing system

Improvement of ECG processing system. m 5151117 Yumiko Kimezawa. Outline. Current Work Bug of SW Failed paths error of HW Future Work. Current Work. Modification of multi-core system so that the system processes ECG signals block by block

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Improvement of ECG processing system

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  1. RPS Improvement of ECG processing system m5151117 Yumiko Kimezawa

  2. Outline RPS • Current Work • Bug of SW • Failed paths error of HW • Future Work

  3. Current Work RPS • Modification of multi-core system so that the system processes ECG signals block by block • - The task is for making previous system that processes ECG signals sample by sample simpler

  4. Bugs of Software RPS • Modification of software in order to process ECG signals block by block • - Only Master module is changed • Not operated • Master module starts processing ECG signals but PPD module doesn’t start that • It will be shown that it’s not mutexproblem

  5. Failed paths error of HW RPS Compilation report Not operational: Clock Skew > Data Delay There were 44 failed paths

  6. Failed paths error of HW RPS Two approaches to solve the problem • Adding system ID core Remain the same • Adding PLL and using global clock Failed paths Reduced from 44 to22

  7. Failed paths error of HW RPS • The number of failed paths hardware of hardware is reduced but ECG processing system is not executed • Above mentioned failed paths may be in previous system Mr. Haga designed • I can’t solve that the errors involved in modified ECG processing system or not

  8. Future Work RPS • Execution of implemented ECG processing system

  9. Future Work GT2010 DMA controller will be added between filtered data mem and shared mem : Data flow : Control signal Ethernet PHY JTAG UART LED Graphic LCD DMA Controller Filtered Data Memory TSE MAC LED Controller Graphic LCD Controller ECG Data Rom Slave CPU Slave CPU Memory Avalon Bus Master CPU TX SGDMA Timer Master CPU Memory FIR Filter Shared Memory Timer Ethernet Module PPD Module Master Module

  10. Future Work GT2010 Implementation of Ethernet module is difficult for me : Data flow : Control signal Ethernet PHY JTAG UART LED Graphic LCD DMA Controller Filtered Data Memory TSE MAC LED Controller Graphic LCD Controller ECG Data Rom Slave CPU Slave CPU Memory Avalon Bus Master CPU TX SGDMA Timer Master CPU Memory FIR Filter Shared Memory Timer Ethernet Module PPD Module Master Module

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