SystemC Study and Modeling of A CPU

1. SystemC Study and Modeling of A CPU 魏君任 謝宜政 R92943101 林家慶 R92943085

2. Outline • Introduction to SystemC(林家慶) • A Simple example with SystemC(謝宜政) • Modeling of a CPU(魏君任)

3. Modules Ports SC_MODULE(fifo) { sc_in<bool> load; sc_in<bool> read; sc_inout<int> data; sc_out<bool> full; sc_out<bool> empty; }

4. Module Signals • Signals can be local to a module, and are used to connect ports of lower level modules together. • These signals represent the physical wires that interconnect devices on the physical implementation of the design. • Signals carry data, while ports determine • the direction of data from one module to another. • Signals aren’t declared with a mode such as in, out, or inout.

5. Positional mapping

6. Named mapping

7. Internal Data Storage

8. Process • Process are the modules that provide functionality and called whenever these signals the process are sensitive to change value. • Processes have sensitivity lists, i.e. a list of signals that cause the process to be invoked, whenever the value of a signal in this list changes. • To trigger a process a signal in the sensitivity list of the process must have an event occur. The event on the signal is the triggering mechanism to activate the process. • Process --Method process --Thread process --Cthread process

9. Method process

10. Thread&Cthread process • Thread Process can be suspended and reactivated. • The Thread Process can contain wait() functions that suspend process execution until an event occurs on one of the signals the process is sensitive to. • An event will reactivate the thread process from the statement the process was last suspended. ------------------------------------------------------------------------------------------------------------------- • Clocked Thread Processes are only triggered on one edge of one clock, which matches the way hardware is typically implemented with synthesis tools.

11. Thread process example

12. Constructor • The module constructor creates and initializes an instance of a module. • The instance name of the module is passed to the constructor at instantiation time.

13. Part2:Transceiver Model 謝宜政

14. Simple SystemC example: Simplex Data Protocol Generates Timeout Events Timer Packets Channel Display Transmit Receive acknowledge Generated the packets by a function Goal: mapping to expected CPU block

15. Port connect start Timer start_timer timeout rpackin dout tpackin tpackout rpackin Receiver Display Transmit channel din tpackin tpackout rpackout rpackout clock

16. Simple SystemC construct Some Block #Include *.h ………….. Implementation: Method,process,case.. Port connect & Data type Constructor For initializing

17. Define Packet structure // packet.h file #ifndef PACKETINC #define PACKETINC #include "systemc.h“ struct packet_type { int seq; // identify the sequence number of the packets int retry; // the number of times the packet has been sent Packets 1 2 3 4 5 ……… Channel Transmit

18. Ex: Transmit Module (1) timeout start_timer Ports sc_in<packet_type> tpackin; // input port sc_in<bool> timeout; // input port sc_out<packet_type> tpackout; // output port sc_inout<bool> start_timer; // inout port sc_in<bool> clock; // input port tpackin Transmit tpackout clock // Constructor SC_CTOR(transmit) { SC_METHOD(send_data); // Method Process sensitive << timeout; sensitive_pos << clock; framenum = 1; \\ initializes the variables retry = 0; start = false; buffer = get_data_fromApp(); } }; Reset for initializing Verilog,VHDL

19. Transmit Module (2) Send_data() 1.Check first if timeout is true 2.Check to see if the current value of tpackin is equivalent to the old value Get_data_fromApp() tpackout Timer Rand() //random number to generate a new data value to send Channel else { packin = tpackin; if (!(packin == tpackold)) { if (packin.seq == framenum) { buffer = get_data_fromApp(); framenum++; retry = 0; } tpackold = tpackin; To see if an acknowledgement Packet was received If the value differ tpackin ,copy it to local “packin” tpackin

20. Architecture CPU Memory Fetch Decode Instruction Cache Execute FPU Data Cache DSP

21. Modeling A CPU Using SystemC 魏君任

22. Simulation • Starts by calling sc_start() from sc_main(). • sc_start(-1): A negative value to this function makes the simulation to continue indefinitely. • Stop by calling sc_stop(). • Calling sc_simulation_time() to determine the current time during simulation. • Debuging: The value printed is the current value, not a value just written to it.

23. Asynchronous event clock = 1; sc_cycle(5); reset = 1; sc_cycle(5); :

24. Asynchronous event clock = 0; sc_cycle(5); clock = 1; sc_cycle(10); reset = 0; sc_cycle(5);

25. Tracing Waveforms • File formats: VCD, WIF and ISDB. • VCD file: sc_trace_file * my_trace_file; my_trace_file = sc_create_vcd_trace_file (“file_name”); : sc_close_vcd_trace_file (my_trace_file); • WIF file: sc_trace_file * my_trace_file; my_trace_file = sc_create_vcd_trace_file (“file_name”); : sc_close_wif_trace_file (my_trace_file);

26. Tracing Variables and Signals of Aggregate Type struct bus { unsigned address; bool read_write; unsigned data; } void sc_trace(sc_trace_file *tf, const bus& v, const sc_string& NAME) { sc_trace(tf, v.address, Name + “.address”); sc_trace(tf, v.read_write, Name + “.rw”); sc_trace(tf, v.data, Name + “.data”); } • Traces the data structure by tracing individual fields of the structure.

27. Tracing Variable and Signal Array void sc_trace(sc_trace_file *tf, sc_signal<int> *v, const sc_string& NAME, int len) { char stbuf[20]; for (int i = 0; i< len; i++) { sprintf(stbuf, “[%d]”, i); sc_trace(tf, v[i], NAME + stbuf); } }

28. Processes Process causes other processes to excute by assigning new values to signals. • Method: SC_METHOD(method_name) • Thread: SC_THREAD(thread_name) can be suspended (wait()) until an event occurs. • Clocked Thread: SC_CTHREAD(thread_name) are only triggered on one edge of one clock.

29. Data structure • bios = system bios data • icache = initial instruction cache • dcache = initial data cache • register = initial register values

30. Instruction set • Arithmetic (x01~x08) • Logical (x09~x0e) • Transfer (x0f, x4d, x4e, x0f1) • Branch (x10~x18) • Floating point (x29~x2c) • DSP (x31~x37) • OS (x00, x0e0, x0f0, x0ff)

31. Instruction format op2 dest OPcode op1 immediate value 31 28 24 20 16 12 8 4 0

32. Partitioning • Running the algorithm and measuring the cycles it takes. • Determining the complexity (cost) of each part of the algorithm. • Implementing some part of the algorithm (by modeling using SystemC).

33. Architecture CPU Memory Fetch Decode Instruction Cache Execute FPU Data Cache DSP

34. Classes CPU Instruction cache (Hex) fetch decode icache exec Data cache (Hex) dcache FPU DSP

35. Spiral-like model Design architecture Develop application Map application to architecture Analyze Modify: mapping, architecture and application Continue refining to lower level unit

36. Design Methodology SystemC Model Simulation Refinement Synthesis

38. System spec. • Behavioral spec. • Modeling • Validation • Simulation • Verification • Partition (Estimation) • Scheduling • Synthesis