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Unified Approach to Modulo-(2n±1) Adder Design

This paper discusses a unified approach to designing modulo-(2n±1) adders based on signed-LSB representation of residues, aiming for correctness and fault tolerance. It explores the use of standard arithmetic building blocks and configurable RNS processors. The study covers background on various modulo-adders, conversion to/from binary, weighted representation, and applications in fault-tolerant RNS processors. The approach simplifies design exploration, testing, and verification, offering greater confidence in correctness.

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Unified Approach to Modulo-(2n±1) Adder Design

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  1. Unified Approach to the Design of Modulo-(2n ± 1) Adders Based on Signed-LSB Representation of Residues • BehroozParhami • Dept. Electrical & Computer Engr. • Univ. of California, Santa Barbara, USA • parhami@ece.ucsb.edu Ghassem Jaberipur Dept. Electrical & Computer Engr. Shahid Beheshti Univ., Tehran, Iran jaberipur@sbu.ac.ir 19th IEEE International Symposium on Computer Arithmetic Portland, Oregon, USA, June 8-10, 2009

  2. Outline • Introduction • Background • Signed-LSB Representation • New Modulo-(2n ± 1) Adders • Mod-(2n + 1) Adder • Mod-(2n – 1) Adder • Conversion from/to Binary • Comparisons & Applications • Conclusion

  3. Introduction • Renewed interest in RNS arithmetic • Separate designs for mod-(2n ± 1) and mod-2n • Error-prone and labor-intensive optimizations • New signed-LSB representation of residues • Sole use of standard arithmetic building blocks • Greater confidence in correctness • Configurable RNS processor for fault tolerance

  4. Background: Mod-(2n – 1) Addition • Mod-m: • Mod-(2n–1):

  5. Background: Symbols Used

  6. Background: Mod-2n Adder

  7. Background: Mod-(2n – 1) Adders • Kalamboukaset al., 2005 RPP modulo 255 adder TPP modulo 255 adder

  8. Background: Mod-(2n + 1) Addition • Mod-(2n+1): • W' is difficult to compute, therefore, let

  9. Background: Mod-(2n + 1) Adders • Efstathiou, et al., 2004 Flaw: Sn is wrong

  10. Background: Mod-(2n + 1) Adders • The corrected mod-257 TPP adder • More area • Same Latency

  11. Background: Dim-1 Representation • Diminshed-1 mod-(2n+ 1)

  12. Signed-LSB Representation • Faithful representation of [–1, 2n – 1] • Problem: Mixed posibits and negabits: A + B

  13. Universal Full Adders • Full adder can compress mixed posibits and negabits ||X1 + X2 + x3|| = X1 – 1 + X2 – 1 + x3 = 2c + s – 2 = ||2C + s||

  14. New Modulo-(2n + 1) Adder

  15. Mod-(2n+ 1) Signed-LSB Addition

  16. New Mod-(2n – 1) Adder

  17. Mod-(2n + 1) vs. Mod-(2n – 1)

  18. Weighted representation Conversion from/to Binary • Conversion of input to residue representation is very simple • Fast residue-to-binary converters implement the Chinese remainder theorem via CSAs Signed-LSB representation Weighted representation

  19. Applications • Fault-tolerant RNS processor

  20. Comparison: Gate-Level Analysis

  21. Comparison: Synthesis Results

  22. Conclusion • Implementing mod-(2n – 1) and mod-(2n + 1) addition using generic CSA and binary adders • Easier/faster exploration of the design space • Simpler testing and verification • Greater confidence in design correctness • Configurable modular adders (fault tolerance) • Potential for less complex modular subtractors and modular multipliers

  23. Questions?The authors gratefully acknowledge the assistance of Mr. SaeedNejati and Ms. HaniehAlavi.G. Jaberipur also acknowledges support from IPM School of Computer Science and from ShahidBeheshti University.Supplement at: www.ece.ucsb.edu/~parhami/publications.htm

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