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EEE2243 Digital System Design Chapter 6: RTL Design by Muhazam Mustapha, April 2012

EEE2243 Digital System Design Chapter 6: RTL Design by Muhazam Mustapha, April 2012. Learning Outcome. By the end of this chapter, students are expected to understand the principle of RTL design. Chapter Content. Principle of RTL Design Example (Soda / Soft Drink Dispenser). RTL Design.

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EEE2243 Digital System Design Chapter 6: RTL Design by Muhazam Mustapha, April 2012

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  1. EEE2243Digital System DesignChapter 6: RTL Designby Muhazam Mustapha, April 2012

  2. Learning Outcome • By the end of this chapter, students are expected to understand the principle of RTL design

  3. Chapter Content • Principle of RTL Design • Example (Soda / Soft Drink Dispenser)

  4. RTL Design

  5. RTL Design RTL stands for “Register Transfer Level” RTL design is the level of digital system design that involves the datapath components and the routing of the data (information) between the components with an addition of a CENTRALIZED controller In this chapter we will see the general steps that involves in RTL design

  6. Steps

  7. Soda Dispenser Example

  8. Examples from text book The Vahid’s and Khalil’s text book provides many examples for you to study It is up to you read them as we won’t have enough time to cover all examples We will only discuss the soda dispenser example from Vahid’s text book

  9. Soda Dispenser Problem Specification: c: bit input, 1 when coin deposited a: 8-bit input having value of deposited coin s: 8-bit input having cost of a soda d: bit output, processor sets to 1 when total value of deposited coins equals or exceeds cost of a soda 25 s s a a 25 50 1 1 0 0 c c Soda Soda d d dispenser dispenser 0 0 processor processor 0 tot: 50 tot: 25 1

  10. Soda Dispenser: Step 1 Capture High Level State Machine: • Declare local register tot • Init state: Set d=0, tot=0 • Wait state: wait for coin • If see coin, go to Add state • Add state: Update total value: tot = tot + a • Remember, a is present coin’s value • Go back to Wait state • In Wait state, if tot >= s, go to Disp(ense) state • Disp state: Set d=1 (dispense soda) • Return to Init state c Add I nit Wait tot=tot+a c’*(tot<s) d=0 tot=0 Disp d=1

  11. Soda Dispenser: Step 2 Create Datapath: s a tot_ld ld tot tot_clr clr 8 8 8 8-bit 8-bit tot_lt_s adder < 8 Datapath • Need tot register • Need 8-bit comparator to compare s and tot • Need 8-bit adder to perform tot = tot + a • Wire the components as needed for above • Create control input/outputs, give them names

  12. Soda Dispenser: Step 3 Connect Datapath to a Controller: • Controller’s inputs • External input c (coin detected) • Input from datapath comparator’s output, which we named tot_lt_s • Controller’s outputs • External output d (dispense soda) • Outputs to datapath to load and clear the tot register s a 8 8 c d tot_ld tot_clr Controller Datapath tot_lt_s

  13. Soda Dispenser: Step 4 Derive the Controller’s FSM: s a tot_lt_s’ c’* tot_ld ld tpt tot_clr clr Inputs: : c , tot_lt_s (bit) Outputs: d , tot_ld , tot_clr (bit) 8 tot_ld 8 8 c c Add tot_clr tot_lt_s d 8-bit I nit W ait 8-bit tot_ld=1 tot_lt_s adder < * c ’ tot_lt_s d=0 8 tot_clr=1 Datapath Disp d=1 Controller s a 8 8 • Same states and architectures as high-level state machine • But set/read datapath control signals for all datapath operations and conditions using the state and input values c d tot_ld tot_clr Datapath Controller tot_lt_s

  14. Soda Dispenser: Completing the design: • Implement the FSM as a state register and logic

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