1 / 22

Reliable Data Storage using Reed Solomon Code

Reliable Data Storage using Reed Solomon Code. Supervised by: Isaschar (Zigi) Walter Performed by: Ilan Rosenfeld, Moshe Karl Spring 2004. Midterm Presentation. Problem:. Cosmic radiation in space causes bit-flips, and therefore valuable information could be lost. Solution:.

zed
Download Presentation

Reliable Data Storage using Reed Solomon Code

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Reliable Data Storage using Reed Solomon Code Supervised by:Isaschar (Zigi) WalterPerformed by:Ilan Rosenfeld, Moshe Karl Spring 2004 Midterm Presentation

  2. Problem: Cosmic radiation in space causes bit-flips, and therefore valuable information could be lost. Solution: All data stored will first be encoded via a Reed Solomon Encoder. A Reed Solomon Decoder will be used when data retrieval is required.

  3. Hardware Resources Memec Design Virtex II Pro Development Kit Xilinx Virtex II Pro RocketIO comm. ports

  4. Software Tools • HDL Designer • ModelSim • Embedded Development Kit

  5. Basic Project Function Reed Solomon Encoder Storage Device Reed Solomon Decoder Hi res Hi freq. input data (possibly) corrupted data (hopefully) corrected data

  6. System Block Diagram PowerPC Memory Controller SDRAM Camera PLB CPU offload unit Rocket I/O Storage RS Encoder RS Decoder

  7. First Semester Goals • In-depth acquaintance with the development environments • Implementing the Reed Solomon cores as slaves on the bus Done! Undergoing...

  8. First Semester Goals – cont. PowerPC Memory Controller SDRAM PLB2OPB Bridge PLB OPB UART IPIF IPIF IPIF RS Encoder RS Decoder FIFO Hyperterminal on DIGLAB PC

  9. First Semester Goals – cont. • The PLB clock frequency is 100MHz • If we perform an 8-bit write per clock cycle to one encoder we can expect a 0.8Gbps throughput out of the encoder. • Higher throughput can be achieved by: • Writing more than 8-bits per cycle (which comes on the expense of encoder work freq) • Using multiple encoders in one IP block. If 32-bit words are to be encoded in the 100MHz frequency then we are limited by the 3.125 Gbps per channel RocketIO rate.

  10. IPIF The IPIF is (as its initials suggest) an interface between the bus and the IP. It takes care of the transaction protocols on the bus and simplifies access to the IP. It also enables special features such as S/W Resetting, User Logic address ranges, interrupts, Bursting, DMA support and more.

  11. IPIF – continued

  12. Bus Transactions Bursting enables us to transfer data with a higher throughput!

  13. Reed Solomon cores • When creating the cores using Xilinx CoreGen, the following parameters are needed: • k: number of symbols per data block (to be encoded) • n: total number of output symbols (original data + check symbols) • s: number of bits per symbol The Reed Solomon code can detect n-k symbol errors and correct (n-k)/2.

  14. RS cores • We have chosen k=239, n=255, s=8, which are similar to G. 709 standard.

  15. RS Cores - Detailed

  16. FIFO Between the encoder and the decoder we have put a Xilinx Synchronous FIFO. The FIFO also has an IPIF interface to the PLB connected to its outputs, in order to look at the intermediate data. For this we have chosen a 1024x8bit FIFO.

  17. Original 1st Semester Schedule • 4 weeks (done): study the development environments, the Virtex II Pro and PowerPC. Building a tutorial application using the CPU. • 1 week: Study the Reed Solomon cores. • 1 week: Study the PLB Bus. • 2 weeks: Building a test application for connection to the bus. • 6 weeks: Designing the described system, simulating, implementing and debugging. Done! Done! Done! Done! Undergoing...

  18. 1st Semester: Remaining Weeks • We have already connected the FIFO and Encoder to the system. • The following still needs to be done: • 1 week: Testing the Encoder and FIFO • 1 weeks: Connecting the Decoder • 2 weeks: Testing the whole system. • 3 weeks: • Building a basic RocketIO application. • Possible optimization of the system: • Using more PLB data lines. • Using multiple RS cores simultaneously. • Using burst transactions on the bus.

  19. Second Semester Goals • Building a CPU offload unit that will be a master on the PLB, perhaps using the DMA capability of the IPIF. • Using another development board to simulate a storage device. • Performing fast and reliable data transfers between the two boards using the RocketIO ports.

  20. Second Semester GoalMain System Diagram PowerPC Memory Controller SDRAM UART, etc. PLB2OPB Bridge OPB PLB CPU offload unit Second Development Board (simulating storage device) Rocket I/O RS Encoder RS Decoder

  21. Second Semester GoalStorage Simulation Diagram PowerPC Memory UART, etc. PLB2OPB Bridge OPB PLB Main Development Board Rocket I/O

  22. Thank you

More Related