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Cumulative Design Review: Interactive Teaching Device April 8 th , 2005

Cumulative Design Review: Interactive Teaching Device April 8 th , 2005. Lance Haney Micah Nance Nathan Young. Important Persons. Client Dr. Aaron Collins Technical Advisor Dr. John Reece Project Manager Dr. Phillip Olivier. Overview. PDR Review Delivered Design Hardware Software

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Cumulative Design Review: Interactive Teaching Device April 8 th , 2005

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  1. Cumulative Design Review:Interactive Teaching Device April 8th, 2005 Lance Haney Micah Nance Nathan Young

  2. Important Persons • Client • Dr. Aaron Collins • Technical Advisor • Dr. John Reece • Project Manager • Dr. Phillip Olivier

  3. Overview • PDR Review • Delivered Design • Hardware • Software • Demonstration • Budget • Conclusion • Recommendations

  4. Client Requirements • Update ECE 424 and ECE 426 • Use state of the art technology • Prepare for new industry trends • Deliver teaching device • Deliver lab manual

  5. Feasibility Criteria • Low budget ($300 maximum) • Compatible with Win98 or WinXP • Applicable to ECE 424 and ECE 426

  6. PDR Design Alternatives • SOPC with RTOS • SOPC without RTOS • Microcontroller with RTOS • Microcontroller without RTOS • VHDL

  7. Design Selected - PDR Phase • Selected SOPC with RTOS Design • NIOS II Evaluation Edition • MicroC/OS-II feature disabled • Design Change • SOPC without RTOS • Design Addition • Implemented VHDL Design

  8. Why SOPC? • One chip • Simplified design • Less hardware • Supports VHDL & current curriculum • Nios II Soft-core Processor • C/C++ • Assembly • Expedite upgrades

  9. Delivered Design • VHDL Implementation • SOPC with Nios II • UP3 Development Board • External Hardware Assembly • Lab Manual

  10. UP3 Development Board • RAM • 11.25 KB on-chip • 128 KB external • 48 MHz clock VGA Port Parallel Port Expansion Headers Cyclone FPGA External RAM USB Port Serial Port On Board Pushbuttons On Board LEDs LCD Display

  11. External Hardware Assembly

  12. Delivered System

  13. System Implementation Alternatives • VHDL • Efficient use of logic elements • 1% Logic Elements Used • Nios II Soft-core Processor with C code • Embedded Processor • High Level Language • 33% Logic Elements Used • 49% Total On-chip Memory Used

  14. VHDL Design

  15. C Code Software Design

  16. Nios II Configurations

  17. Nios II Debugging Options

  18. System Demonstration • VHDL Design • Nios II Soft-core Processor with C Code Design

  19. Budget • Prototype Cost

  20. Budget • Lab Implementation

  21. Conclusion • Utilize Altera UP3 Development Board • Low cost • Versatile • Expandable • Innovative • Altera Software Package • Reasonable learning curve • User friendly • Versatile

  22. Recommendations • 12 Workstations • Altera UP3 Development Board • External Hardware • Windows XP • Integration into ECE 424/426 curriculum

  23. Summary • PDR Review • Delivered Design • Demonstration • Budget • Conclusion • Recommendations

  24. Questions?

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