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Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction

Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction. Dianwei Hu and Dong Xiang Tsinghua University Beijing, China. Qiang Xu The Chinese University of Hong Kong. Outline. Background Pattern-Directed Virtual Partitioning Routing-Aware Virtual Partitioning

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Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction

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  1. Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction Dianwei Hu and Dong Xiang Tsinghua University Beijing, China Qiang Xu The Chinese University of Hong Kong

  2. Outline • Background • Pattern-Directed Virtual Partitioning • Routing-Aware Virtual Partitioning • Experimental Results • Conclusion

  3. Test Power • Toggle rate in test mode may be significantly higher than that in functional mode • Excessive accumulated power -> permanent damage • Excessive instantaneous power -> test yield loss Excessive test power is a major concern!

  4. Prior Work on Test Power Reduction • Scan chain manipulation: • Scan chain partitioning (e.g., Whetsel ITC’02) • Scan chain reordering (e.g., Bonhomme ITC’02) • Test vector manipulation: • Power-aware ATPG (e.g., Wang TCAD’98) • Low-power X-filling (e.g., Butler ITC’04, Wen ITC’05) • Test vector reordering (e.g., Dabholkar TCAD’98) • Test scheduling • Circuit modification

  5. wrapper Scan chain Scan chain Scan chain P1 wrapper Scan chain Scan chain P2 Circuit Partitioning for Test Power Reduction Tester Circuit under Test Data Glue Logic SE TCK

  6. Observations and Motivation • Test patterns’ power consumptions vary significantly • Only a few “care-bits” necessary for a test pattern to detect all the faults covered by it • Applying high-power patterns at a partitioned subcircuit containing all their care-bits reduces test power without fault coverage loss

  7. Virtual Circuit Partitioning Circuit under Test Scan chain Scan chain Scan chain P1 Glue Logic High-power Patterns Low-power Patterns Scan chain Scan chain P2

  8. Problem Definition • How to partition the circuit such that the “care-bits” of as many as possible high-power patterns belong to a single partition?

  9. Design Flow Start (with given specified patterns) Rank test patterns based on capture power Fault simulation Identify care-bits for the high-power patterns Iteratively partition the circuit Yes Meetconstraints No End

  10. Care-Bits Identification • Let low-power patterns detect as many faults as possible • Response care-bits: fault simulation • Stimulus care-bits: limited implication • Cost function, depends on: • Care-bits selected by previous patterns • Comparison between different response care-bits

  11. Care-Bits Identification 0(1) 0 1 1 Response Carebits 1(0) sa-0 0 1(0) 1

  12. Care-Bits Identification Stimuli Carebits 0(1) 0 1 1 1(0) sa-0 0 1(0) 1

  13. Care-Bits Identification 0(1) 0 1 1 1(0) sa-0 0 1(0) 1 Stimuli Carebits

  14. Iterative Partitioning Lowpower High power P2 P1 P3 Patterns Fault simulation Faults F2 F3 F4 F1

  15. P2 P3 P1 F2 F3 F4 F1 Iterative Partitioning Lowpower High power Patterns Faults R1 R2 I1 R1 I1 I1, I2

  16. P2 P3 P1 F2 F3 F4 F1 Iterative Partitioning Lowpower High power Patterns Faults R4 I1, R1 I3, I4, R4 I3, I4

  17. P2 P1 F2 F1 Iterative Partitioning Lowpower High power P3 Patterns Faults F3 F4 R1 I1, R1, I2 I1, R1 I3, I4, R4 I2

  18. P2 P3 P1 F2 F3 F4 F1 Iterative Partitioning Lowpower High power Patterns Faults R1 R1 R3 I1, R1, I2 I3, I4, R4 I2 I1, I2 I3, I4

  19. Routing-Aware Partitioning • Partitioning significantly affects scan chain routing cost • Solution: constraint-driven partitioning • Model the spreadness of the scan FFs • Divide the circuit layout into sub-regions • Routing either horizontally or vertically in a snake-like way

  20. RA-Partitioning Design Flow Start (with given specified patterns) Rank test patterns based on capture power Fault simulation Identify care-bits for the high-power patterns Iteratively partition the circuit with routing consideration Iteratively partition the circuit Yes Meet constraints No End

  21. Routing-Aware Partitioning – Cont. H (0,220) (250,220) d CUT (150,180) 25 +=30 V c 5 b (130,100) 45 (80,100) +=130 a (40,40) 85 (0,0) (250,0)

  22. Routing-Aware Partitioning – Cont. H (0,220) (250,220) d CUT (150,180) 70 V c b 10 10 (130,100) (80,100) 70 +=90 a (40,40) (0,0) (250,0)

  23. Experimental Result – s38417 (stuck-at) Routing-Aware Partitioning Iterative Partitioning

  24. Experimental Result – s38584 (broadside) Routing-Aware Partitioning Iterative Partitioning

  25. Power comparison for stuck-at • Average power with VP: 49.13% • Average power with RA-VP: 57.67%

  26. Wire length comparison for stuck-at • Average wire length with VP: 142.52% • Average wire length with RA-VP: 109.62%

  27. Power comparison for broad-side • Average power with VP: 63.59% • Average power with RA-VP: 68.28%

  28. Wire length comparison for broad-side • Average wire length with VP: 141.68% • Average wire length with RA-VP: 112.57%

  29. Conclusion • Excessive test power is a major concern today • We propose routing-aware circuit virtual partitioning technique for test power reduction • without adding test wrappers • without fault coverage loss • with small scan chain routing cost

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