Wei-Cheng Lien 1 , Kuen-Jong Lee 1 and Tong-Yu Hsieh 2

1. A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume Wei-Cheng Lien1, Kuen-Jong Lee1 and Tong-Yu Hsieh2 1Dept. of Electrical Engineering, National Cheng Kung Univ., Taiwan 2Dept. of Electrical Engineering, National Sun Yat-sen Univ., Taiwan

2. Outline • Introduction • Previous Work • Proposed Concurrent Multiple Test Embedding Procedure • Experimental Results • Comparisons • Conclusions

3. Employ some specific on-chip test structure to test a circuit itself. Pseudo Random Testing Mixed-mode BIST Reseeding Mapping Logic Deterministic BIST Twisted Ring Counter (TRC) Introduction – Logic Built-In Self-Test (BIST) ROM Circuit Under Test L F S R Mapping Logic • In this paper we will focus on test-per-clock LFSR reseedingalgorithm to reduce test sequence length and test data volume.

4. Previous Reseeding Algorithms • Previous test-per-clock reseeding methods mainly comprise 3 steps. • Step 1: Seed Selection • Select one pattern as an initial seed from a given test set. • Step 2: Test Sequence Generation • Generate a fixed length of test sequence. • Step 3: Test Set Embedding • Select pattern one-by-one. • Embed as many patterns as possible. (Pattern-Oriented) • Go back to Step 1 if no patterns in the remaining test set can be embedded. Pattern 2 (Seed) A pre-defined partially- specified test set Step 1 … Pseudo Random Pattern 1 Pattern 1 Pattern 3 Pseudo Random Pattern 2 Pattern 2 Step 2 Pseudo Random Pattern 3 Step 3 Pattern 3 … Pseudo Random Pattern N

5. Features of Proposed Reseeding Algorithm • Compared with previous reseeding algorithms, our reseeding technique (called concurrent multiple test embedding method) has the following distinguishing features to determine one seed. • Step 1: Test Sequence Generation • Start with a fully-unspecified pattern as an initial seed. • Incrementally increase the test sequence length only when necessary. • Step 2: Candidate Pattern Generation • Directly fill the X-bits of the newly-added test sequence to generate candidate patterns for test embedding. • Step 3: Test Set Embedding • Embed multiple candidate patterns at one time. • Detect as many undetected faults as possible (Fault-Oriented)

6. Concurrent Multiple Test Embedding Procedure Apply random patterns to extract hard-to-detect faults from FT and store them to FHD A testable faults list FT i ← 1 seed determination process Perform seed determination process to generate one seed Si for FHD and drop all detected faults from FHD Test Sequence Generation Candidate Pattern Generation Test Set Embedding Add Si to S No Is FHD empty? i ← i + 1 Yes Perform seed reusing process to reuse all generated seeds in S to drop all detected faults from FT Perform seed determination process to generate one seed Si for FT and drop all detected faults from FT Yes Is FT empty? END No Add Si to S i ← i + 1

7. Equation Pseudo Random Pattern I1 I2 I3 I4 I5 I1 I2 I3 I4 I5 LS1 x x x x x x1 x2 x3 x4 x5 LS2 x x x x x x2⊕x5x1 x2 x3 x4 LS3 x x x x x x1⊕x4x2⊕x5x1 x2 x3 LS4 x x x x x x2⊕x3⊕x5x1⊕x4x2⊕x5x1 x2 LS5 x x x x x x1⊕x2⊕x4x2⊕x3⊕x5x1⊕x4x2⊕x5x1 LS6 x x x x x x1⊕x2⊕x3⊕x5x1⊕x2⊕x4x2⊕x3⊕x5x1⊕x4x2⊕x5 Seed Determination – Test Sequence Generation • Assume the CUT has 5 inputs from I1 to I5, 15 faults from f1 to f15 and P(x) = 1 + x2 + x5. • Use an user-defined input parameter LCS to limit the maximum number of consecutive redundant patterns during test sequence generation. (LCS = 6 in our example)

8. Seed Determination – Candidate Pattern Generation • Specify the X-bits in the newly-added pseudo random patterns to generate candidate patterns for test embedding. Candidate Patterns Detect Faults X-filling LS1 x x x x x x 01 x 1 f2 f6f7f15 P1 LS2 x x x x x P2 x 1 0 0 0 f5 f9f10f12 LS3 x x x x x P3 x 1 1 0 1 f1 f3f14 LS4 x x x x x P4 0 x 0 x 1 f4f11 LS5 x x x x x P5 1 1 1 1 x f8 LS6 x x x x x P6 1 x 0 x 1 f13 6 pattern pairs (P1,LS1) (P2,LS2) (P3,LS3) (P4,LS4) (P5,LS5) (P6,LS6)

9. Compatibility Graph P2,LS2 P1,LS1 P4,LS4 6 candidate pattern pairs P3,LS3 P6, LS6 P5,LS5 Seed Determination – Test Set Embedding(1/3) Seed Solution of Each Pattern Pair LS1 x x x x x x 01 x 1 x2 = 0 x3 = 1 x5 = 1 P1 LS2 x x x x x P2 x 1 0 0 0 x1 = 1 x2 = 0 x3 = 0 x4 = 0 LS3 x x x x x P3 x 1 1 0 1 x1 = 1 x2 = 0 x3 = 1 x5 = 1 LS4 x x x x x P4 0 x 0 x 1 x2 = 1 x3 = 0 x5 = 1 LS5 x x x x x P5 1 1 1 1 x x2= 0 x3= 0 x5= 1 x1⊕x4= 1 LS6 x x x x x P6 1 x 0 x 1 x1= 1 x3= 1 x2⊕x5= 1 6 candidate pattern pairs (P1,LS1) (P2,LS2) (P3,LS3) (P4,LS4) (P5,LS5) (P6,LS6)

10. Detect Faults Weight of (Pi, LSj) f2 f6f7f15 4+(3+1)/2 = 6 P1 Weight of (P1, LS1) = 4 (#faults detected by P1) + {3 (#faults detected by P3) + 1 (#faults detected by P6) } /2 = 6 P2 f5 f9f10f12 4+(1)/1 = 5 P3 f1 f3f14 3+(4+1)/2 = 5.5 P4 f4f11 2 P5 f8 1+(4)/1 = 5 P6 f13 1+(4+3)/2 = 4.5 Seed Determination – Test Set Embedding (2/3) Compatibility Graph Weight = 6 Weight = 5 P2,LS2 P1,LS1 Weight = 2 P4,LS4 P3,LS3 P6, LS6 P5,LS5 Weight = 5.5 Weight = 4.5 Weight = 5

11. Weight = 5 P2,LS2 Weight = 2 P4,LS4 P5,LS5 Weight = 5 x2 = 0 x3 = 1 x5 = 1 (P1, LS1) Seed Solution x1 = 1 x2 = 0 x3 = 1 x5 = 1 (P3, LS3) x1 = 1 x2 = 0 x3 = 1 x5 = 1 Update All Patterns (P6, LS6) x1= 1 x3= 1 x2⊕x5= 1 101 x 1 LS5 x 0 x 11 LS1 LS3 x 1 1 0 1 LS6 1 x 0 x 1 LS2 1 1 0 1 x LS4 0 x 110 Seed Determination – Test Set Embedding(3/3) • Embed multiple candidate patterns to detect most undetected faults at one time. Compatibility Graph Weight = 6 P1,LS1 P1,LS1 P3, LS3 P3,LS3 P6, LS6 P6, LS6 Weight = 4 Weight = 5.5 Weight = 1 Weight = 4 Weight = 4.5

12. 101 11 4 LS1 Detect Faults f4f11 0 LS2 1 1 0 1 1 FC=10/15=67% LS3 01 1 0 1 3 LS4 00110 0 P1 0 x 0 x 1 LS5 0 0 0 11 2 X-filling LS6 1 0001 1 f5 f9f10f12 LS7 1 1000 4 FC=14/15=93% LS8 1 1 100 0 f8 LS9 1 1 110 1 FC=15/15=100% Seed Determination – Termination Conditions Fault Coverage (FC) = 8/15 = 53% 7 Undetected Faults = {f4 f5 f8 f9f10 f11f12} #detected faults Update All Patterns 101 x 1 4 LS1 0 LS2 1 1 0 1 x LS3 x 1 1 0 1 3 Seed Solution LS4 0 x 110 0 x4 = 1 LS5 x 0 x 11 0 LS6 1 x 0 x 1 1 • Termination Conditions: • All faults are detected. • 2. LCS consecutive patterns can • not detect any new faults even • after applying test embedding. • => Identify a new seed.

13. Seed Reusing Process • We reuse the generated seeds for FHD to detect all testable faults first and drop all faults detected by the generated seeds from FT. • If some testable faults in FT are still undetected, we will further utilize the remaining X-bits in those seeds to detect more faults. • Sort all generated seeds in increasing order of their derived test sequence length. • Select the seed according to their sorting order. • Use the seed determination process againfor the target seed to detect undetected faults in FT. • Terminate until all testable faults are detected. Otherwise, identify more seeds for all remaining faults after considering all current seeds.

14. Experimental Results – ISCAS’85 Benchmarks 100% stuck-at fault coverage is targeted and the input parameter LCS (limit on the number of consecutive redundant patterns) is set to 60. Our method can achieve 100% fault coverage with a small number of seeds (storage data volume) and very short test sequence length (test time).

15. Experimental Results – ISCAS’89 Benchmarks For any ISCAS circuit,our method can detect all testable faults in less than5000 test cycles.

16. Comparisons – LFSR Reseeding Methods [1] E. Kalligeros, et al., "An efficient seeds selection method for LFSR-based test-per-clock BIST,“ ISQED, 2002. [2] E. Kalligeros, et al.,"Reseeding-based test set embedding with reduced test sequences," ISQED, 2005.

17. Comparisons – Mapping-Logic-Based Methods [3] E. Kalligeros, et al., "On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST," JETTA, 2002. [4] Y. Si, et al., "Multiple test set generation method for LFSR-based BIST," ASP-DAC, 2003.

18. Comparisons – TRC-Based Reseeding Methods [5] K. Chakrabarty, et al., "Built-in Test Generation For High-Performance Circuits Using Twisted-Ring Counters," VTS, 1999. [6] S. Swaminathan, et al., "On Using Twisted-Ring Counters for Test Set Embedding in BIST," JETTA, 2001. [7] B. Zhou, et al., "Simultaneous reduction in test data volume and test time for TRC-reseeding," GL-VLSI, 2007.

19. Conclusions • This paper proposes a new test-per-clock LFSR reseeding algorithm that can simultaneously minimize both the storage data volume and the test sequence length. • Experimental results show that • comparing with previous LFSR-based reseeding methods, our method can reduce more than 70% test sequence length with a much smaller number of seeds. • comparing with previous mapping-logic-based BIST methods, our method can save over 50% of test sequence length with comparable area overhead. • comparing with previous TRC-based reseeding methods, 60~99% test sequence length can be reduced by using our method with smaller storage data volume.

20. Thank You Very Much for Your Attention.

21. Experimental Results – IWLS industrial circuits 100% stuck-at fault coverage is targeted and the input parameter LCS (limit on the number of consecutive redundant patterns) is set to 60. The results on IWLS industrial circuitsare even better than those on ISCAS benchmark circuits because less number of redundant faults

22. Experimental Results – Different LCS values 100 stuck-at fault coverage is targeted. LCS: limit on the maximum number of consecutive redundant patterns LCS value increases → storage test data volume decreases test sequence length increases.