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TRD Monitor Tube Readout Electronics: Shaping. Peter Fisher, Bernard Wadsworth, Andrew Werner MIT. 1. i. V. 3.2 V. t. t. ~10 ns. TRD Gas Monitor Tubes: Electronics. Proportional tubes & Fe55 source. Readout front end; Shaping stage. Multi-Channel Analyzer (MCA). MCA8000A. ~ 10 uA.
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TRD Monitor Tube Readout Electronics: Shaping Peter Fisher, Bernard Wadsworth, Andrew Werner MIT Andrew Werner 1
i V 3.2 V t t ~10 ns TRD Gas Monitor Tubes: Electronics Proportional tubes &Fe55 source Readout front end; Shaping stage Multi-Channel Analyzer (MCA) MCA8000A ~ 10 uA 250 ns Andrew Werner 2
Charge Sensitive Amplifier Charge Sensitive Amplifier Charge Sensitive Amplifier Charge Sensitive Amplifier Shaper (CR-RC) Shaper (CR-RC) Shaper (CR-RC) Shaper (CR-RC) 4:1 Analog Mux To MCA Front End Electronics: Overview • Four channels: one digitally selectable at a given time • Expects incoming current pulse of width 10 ns and height 10 uA; Total charge carried by pulse ~ 100 fC • CSA Stage Gain: 10 V/pC • Output scaled from 0 V - 3.2 V; Gaussian pulse with 250 ns width • Runs off of 5V single supply; total DC current draw 60 mA typ, 85 mA max => Static power diss. 300 mW typ, 425 mW max • 146 mV nom. DC offset at output Andrew Werner 3
Simplified Circuit Diagram (1) R2 Vcc R7 + HV C2 D1 C4 R5 R1 C1 - R6 - U1 D2 U2 + C3 Vref Vref + R3 + - R4 Vref Key component values: C1: 1 nF, 3 kV R2: 12 mOhm, C2: 2 pF, tau = 24 uS R3: 1.54 K R4: 80.6 Ohm R5: 910 K C3: 27 pF R6: 9.1 K R7: 27 K C4: 9.0 pF Vcc = +5V Reference is LT1460 (Linear), Vref = 2.5V ± 0.1% U1, U2: OPA357 (TI/BB) Andrew Werner 4
Simplified Circuit Diagram (2) C12 R12 Vcc CH3 S3 U11 ADG708 R11 CH2 S2 - R13 CH1 S1 U12 R13 Vref + CH0 S0 To MCA A0 A1 C11 R14 BIAS NETWORK Component values: R11, R13: 1.0 K R12, R14: 2.0 K All values 1% R13: 100 Ohm U11 is a 8:1 multiplexing switch; one of the inputs is connected to the output by the inputs S0 and S1. U12 eliminates the 2.5V offset and provides output to the MCA Andrew Werner 5
Board Layout • Outsourced development of prototype board; surface mount • Dimensions: 3.25” x 2.75” (82.5 mm x 69.9 mm) • Four layers: Component, Solder, Ground, +5V • Four slots for input capacitors; minimize possibility of dielectric breakdown • Reference placed in cutaway section to minimize noise due to flexure of board Andrew Werner 6
Schedule • Board layout nearly complete, should be sent out for fabrication within this week or the next • Testing, verification to begin soon • Expected final delivery: September • Thanks to Peter Fisher and Bernard Wadsworth of MIT LNS for help and guidance in the circuit design Andrew Werner 7