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A 4-Bit 5GS/s Flash A/D Converter in 0.18 μm COMS

A 4-Bit 5GS/s Flash A/D Converter in 0.18 μm COMS. 班 級：積體所碩一 學 生：許庭耀 指導教授：林志明 老師. Outline. Introduction Architecture of the ADC Circuit Description Simulation Result Layout Advantage of the Proposed ADC Conclusion. Introduction. Time-interleaved architecture

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A 4-Bit 5GS/s Flash A/D Converter in 0.18 μm COMS

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  1. A 4-Bit 5GS/s Flash A/D Converter in 0.18μm COMS 班 級：積體所碩一 學 生：許庭耀 指導教授：林志明 老師

  2. Outline • Introduction • Architecture of the ADC • Circuit Description • Simulation Result • Layout • Advantage of the Proposed ADC • Conclusion

  3. Introduction • Time-interleaved architecture • Two-stage resistor offset averaging gives an ENOB of 3.65 bits.

  4. Introduction Fig.1.Two-stage of averaging resistor networks

  5. Architecture of the ADC Fig. 2. Architecture of the proposed 4-bit flash ADC

  6. Circuit Description 1 Fig. 3. Preamplifier

  7. Circuit Description 2 Fig. 4. The 1st latches

  8. Circuit Description 3 Fig. 5. The 2nd and 3rd latches

  9. Circuit Description 4 Table 1. Binary-Gray-Thermometer code implementation

  10. Circuit Description 5 Fig. 6. The encoder Circuit

  11. Simulation Result

  12. Simulation Result

  13. Simulation Result

  14. Simulation Result

  15. Simulation Result

  16. Simulation Result Table 2. Comparison of the Performance

  17. Layout Fig. 7. Using a ring path for delivery of the input signal to the preamplifier array

  18. Layout Fig. 8. Layout of the ADC

  19. Advantage of the Proposed ADC • All the signals both in the analog part and the digital part are differential. • Overdrive recovery time limits highest ADC clock frequency. • Meta-stability errors

  20. Conclusion • A non-time-interleaved ADC • With no digital calibration technique • More bits

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