Towards minimizing read time for NAND Flash

1. Towards minimizing read time for NAND Flash  Globecom December 5th, 2012 BorjaPeleato, Rajiv Agarwal, John Cioffi (Stanford University)Minghai Qin, Paul H. Siegel (UCSD)

2. Outline • Introduction • NAND Flash write and read • Memory structure • Problem: choosing read thresholds • Progressive read algorithm • Estimating Min-BER threshold • Generating soft information • Results

3. Cell write procedure Control gate Floating gate Dielectric N+ Source N+ Drain P-Type Silicon Substrate

4. Cell read procedure + Control gate Vt = 2V Vt = 1V _ Floating gate Dielectric N+ Source N+ Drain P-Type Silicon Substrate Exact voltage unknown, read returns 1 if Vt < Vcelland 0otherwise

5. Memory structure • Main sources of noise: • Over-programming (and write noise) • Leakage • Inter-Cell-Interference (ICI) Page (~105 cells): write/read unit Block (~128pages): erase unit Noise increases with cell scaling and wear

6. Problem • How do we choose read voltages when noise estimates are not available?

7. Progressive Read Algorithm • Estimate Gaussian noise from noisy cdf samples If then hence Solve for read threshold with min BER t

8. Min BER threshold • Minimum estimation error when reads are close to the means and spread out

9. Soft information • If hard decoding fails, re-use reads for soft decoding • For lower failure rate, reads clustered in uncertainty region… if means and variances are known • For best combined noise estimation and decoding, two reads in each region

10. Result: ½ read operations 4 reads instead of 8 2x speed

11. Thank you!