DYNAMICALLY RECONFIGURABLE SYSTOLIC ARRAY ACCELERATORS: A CASE STUDY WITH EKF AND DWT ALGORITHMS

1. Robert Barnes Utah State University Department of Electrical and Computer Engineering Thesis Defense, November 13th 2008 DYNAMICALLY RECONFIGURABLE SYSTOLIC ARRAY ACCELERATORS:A CASE STUDY WITH EKF AND DWT ALGORITHMS

2. Outline • Introduction & Background • System Design • Results & Conclusions

3. Motivation • Increasing Demands for Spacecraft • Low Power • Fault Tolerant • Flexibility • High Performance • Solution: FPGA

4. General Goals • Flexible Extended Kalman Filter (EKF) System on an FPGA • Adaptable to changing performance requirements (scalable). • System adaptable to other algorithms (DWT). • Outperform RAD750 PowerPC • Explore applications of dynamic reconfiguration.

5. Kalman Filter • To navigate in space an autonomous spacecraft must accurately estimate its state from noisy measurements. • The filter is very flexible • Estimate a system’s state from only a single sensor • Estimate the bias in sensors • Determine an unknown system model • Predict a future states

6. Faddeev Algorithm

7. Extended Kalman Filter

8. Discrete Wavelet Transform Algorithm

9. Systolic Arrays • A network of simple processing elements (PE) which rhythmically process and pass data to nearest neighbours to process larger complex tasks. • Features: • Modularity • Regularity • Locality • Synchronous • Pipelined • Data Reuse

10. Partial Dynamic Reconfiguration

11. Configuration Layout Figure Source: Jeff Carver

12. Other Reconfiguration Methods • JBits • Interface to make changes to the Bitstream • Modular Design Flow • Early Access Design Flow • Improved Modular Design Flow

13. Scaling Methods • Soft scaling • Using conditional variable loops and conditional statements, software can easily be made to scale to different parameters. • Static Hardware Scaling • Using MUXes a hardware architecture can be designed where data can be re-routed to different hardware cores. • Reconfigurable Hardware Scaling • Using partial dynamic reconfiguration the physical size of the systolic array can be scaled.

14. Outline • Introduction & Background • System Design • Results & Conclusions

15. Polymorphic Systolic Array Framework (PolySAF) Co-Processor PolySAF

16. SwitchBox

17. Interface Hierarchy

18. 2D Fadeev Systolic Array

19. Vertical Systolic Array

20. Hardware/Software Mapping

21. DWT Systolic Array

22. Hybrid PDR

23. Mapping & Scaling

24. Outline • Introduction & Background • System Design • Results & Conclusions

25. Floor Planning

26. Floor Planning Sockets

27. Sockets vs Problem Size vs Cycles

28. Comparison with PowerPC

29. Reconfiguration Performance

30. Area Analysis

31. Conclusions & Limitations • A polymorphic systolic array framework (PolySAF). • Programmable switchboxes and protocol to allow dynamic scaling in the array. • Efficient EKF and DWT accelerators • Speedup of at least 4.18x and 6.61x over PowerPC for EKF and DWT. • Integration of bitstream relocation and bitstream compression into a practical system. • 2.7x improvement in reconfiguration time. • A 44% improvement in BRAM usage. • The flexible and simple framework allows this design to host a broad range of algorithms. • Dynamic reconfiguration is powerful, but it is not useful in every application. The trade-offs must be weighed carefully.

32. Questions?

33. Publications • R. Barnes and A. Dasu, “Hardware/software Co-designed Extended Kalman Flter on an FPGA,” in The International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008. • R. Barnes, A. Dasu, J. Carver, and R. Kallam, “Dynamically Reconfigurable Systolic Array Accelerators: A case study with EKF and DWT Algorithms,” Institution of Engineering and Technology (IET) Computers & Digital Techniques. In Review.

34. Misc. • Hours: 4.33wks/month*16months*(>40hours/wk) = ~2771hours • Embedded C: ~6,000 • Verilog Code: ~3,222 • Python: ~1015 • Tools: • EDK • ISE • Modelsim • MatLab • Xpower • PlanAhead • Eclipse • Simics • Python