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HDL-Based Layout Synthesis Methodologies

HDL-Based Layout Synthesis Methodologies. Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {Email: chunghaw@cs.nthu.edu.tw}. Outline. Introduction Timing analysis Design planning RTL timing budgeting

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HDL-Based Layout Synthesis Methodologies

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  1. HDL-Based Layout Synthesis Methodologies Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {Email: chunghaw@cs.nthu.edu.tw}

  2. Outline • Introduction • Timing analysis • Design planning • RTL timing budgeting • A timing-driven soft-macro placement and resynthesis method • Discussion

  3. Why Needs HDL-based Design Methodologies? Design complexity Then Now Schematic capture HDL design specification Component mapping & may be some logic optimization Synthesis Place & route Place & route Layouts Layouts SW : assembly language => high-level language

  4. An HDL-based Design Flow HDL design specification HDL coding styles Applications RTL synthesis Logic synthesis Cell libraries Layout architectures Layout synthesis Layouts

  5. Top-Down Design Methodology HDL design specification Preserving design hierarchy RTL synthesis Bridging the gap between RTL, logic, and layout synthesis Logic synthesis Layout synthesis Layouts

  6. Applications and Layout Architectures • Datapath dominated designs : DSPs and processors. • Control dominated designs: controllers and communication chips. • Mixed type of designs. • Bit-sliced stacks. • Standard cells. • Macro-cell-based. • FPGAs.

  7. Layout-driven Design methodology HDL design specification RTL synthesis Multi-level estimation engine Logic synthesis Back annotation Layout synthesis Layouts

  8. Design Estimation • Timing • Area • Power • Statistic VS. quick-synthesis methods • Analytical VS. constructive methods

  9. Outline • Introduction • =>Timing analysis • Design planning • RTL timing budgeting • A timing-driven soft-macro placement and resynthesis method • Summary

  10. Minimum Cycle Time Critical path delay Clock skew

  11. Timing Analysis • Critical path delay analysis • Clock skew analysis • Timing analysis at different design levels • Delay calculation • Parasitic extraction • Accuracy VS. fidelity

  12. Timing Analysis HDL design spec. HDL specification RTL synthesis Logic equations Logic synthesis Accuracy Complexity Cell-based netlists (Tech. dependent or independent) Layout synthesis Floorplanning and P & R Layouts

  13. RTL and Logic-level Timing Analysis HDL Spec. Macro Macro Macro based Logic equations Outputs Inputs Macro Cell-based netlist Unit and zero delay models for cells and wires

  14. RTL Timing Analysis A Aspect ratio A Aspect ratio HDL design spec. Macro Macro T T Floorplanning Re-synthesis & re-floorplanning Back annotation 3 3 1 1 4 4 2 2

  15. Chip-level Timing Analysis Macro cells • Taken into account inter-macro wiring delays. • Chip-level path enumeration. • Estimation vs. back annotation. Floorplanning Layout extraction Wiring delay

  16. Macro-level Timing Analysis Netlists • Taken into account intra-macro wiring delays. • Path delay enumeration. • Estimation vs. back annotation. P & R Layout extraction Wiring delay information

  17. Accuracy of Timing Analysis Design Stages Accuracy RTL 100+/-50%??? Floorplanning 100+/-25% Placement 100+/-15% Global routing 100+/-7% Detailed routing 100+/-0% Source: DAC’97 Tutorial by Blaauw_Cong_Tsay

  18. Outline • Introduction • Timing analysis • => Design planning • RTL timing budgeting • A timing-driven soft-macro placement and resynthesis method • Summary

  19. Design Planning • Macro definitions • Soft macro generation • Macro placement • Pin assignment

  20. Chip Planning I Soft macros Hard macros

  21. Chip Planning II Soft macros Hard macros

  22. Design Planning Considerations • How much timing, area, and power budgets should be assigned to each macro? • How to generate soft macros? - top-down - bottom-up • How to layout clock and power/ground network?

  23. Delay, area, power constraints ?????????????? Design Budgeting Driving resistance Load capacitance Macro Arrival time Required arrival time RTL Spec. RTL & Logic synthesis Netlists

  24. Design SM SM Soft Macro Generation Partitioning SM SM SM Clustering Based on design hierarchical information

  25. Soft Macro Generation (Cont.) Perform clustering techniques on a flattened netlist Clustering criteria: . Timing . Interconnect

  26. Design Hierarchy Preservation HDLs Verilog design spec. Mod1 Mod2 Mod3 HDL synthesis Macro formation Macro placement Macro to cell placement Initial placement

  27. Clock Network Styles • Mesh: robust, large area and power • Trunk: simple • Tree: min area, many supporting design algorithms

  28. Clock Issues at RTL Critical path is determined from clock skew and skew cannot be determined until placement is completed! How to incorporate clock skew issues into early design planning???? Still an open problem!

  29. RTL Timing Analysis A Aspect ratio A Aspect ratio HDL design spec. Macro Macro T T Floorplanning Re-synthesis & re-floorplanning Back annotation 3 3 1 1 4 4 2 2

  30. Timing-critical Macro Detection HDL Spec. HDL spec. Macro Macro HDL synthesis Critical macro Floorplanning Chip-level timing analysis Back annotation

  31. RTL Design Planning Floorplanning HDL Spec. Macro Macro Back-annotation Delay & area estimations Cell library RTL timing analysis Constructive or analytical method Back-annotation

  32. Outline • Introduction • Timing analysis • Design planning • => RTL timing budgeting • A timing-driven soft-macro placement and resynthesis method • Summary

  33. RTL sign-off Physical-level Synthesis RTL Spec. RTL/logic Synthesis HM SM1 SM2 Chip Layout SM3 Netlists HM RTL Design Budgeting Loop Area Delay Power Budget? Loop Loop

  34. Timing Budgeting Cross-macro timing paths!!! 1 Cycle

  35. Timing Budgeting Issues • How to estimate delay and area from RTL specification??? • After floorplanning? After RTL/logic synthesis? After placement? After routing? • Run time VS. accuracy? • How to distribute timing budget among macros? • No much work has been done in this area!!!

  36. A A A x x x T T T M2 M1 M3 Timing Budgeting for Design Optimization Minimize total area subject to satisfying the timing constraints.

  37. Outline • Introduction • Timing analysis • Design planning • RTL timing budgeting • => A timing-driven soft-macro placement and resynthesis method • Summary

  38. HDL Description Chip Layout A Typical Design Flow for Macro-based Design Back-annotation HDL Synthesis Timing Analysis No OK? Floorplanning Yes P & R

  39. Design Hierarchy Preservation Preserving HDL design hierarchy for soft-macro placement? HDL Description HM M1 HM M_11 M2 SM M_12 HM A complete chip design methodology?

  40. Considerations • How to utilize HDL design-hierarchy information to guide soft-macro placement procedure? • How to integrate design tasks and point tools at different design level to form a complete chip design methodology? • How to exploit the interaction between different design tasks.

  41. Floorplanning & Area Extraction HDL Description Back-annotation SM Placement HDL Synthesis Pre-layout Timing Analysis Structural-tree Construction P & R Post-layout Timing Analysis Chip Layout SM Formation Design Flow for Design Hierarchy Preservation

  42. Structural-tree Construction • The main objective is to preserve the design structural information from an HDL design description for macro formation. Top SM4,5 SM1,2 HM1 SM1 SM2 HM2 SM3 SM4 SM5

  43. Soft macro Formation • Decomposition of large soft macros. - A large macro is too rigid for macro placement. • Clustering of small soft macros. - Many small macros increase the computational complexity.

  44. Soft Macro Placement • Inputs: a set of software macros and the available area for soft macros. • Outputs: the relative location of each soft macro on the layout plane. • 1st step: force-directed-based placement. • 2nd step: Sweeping-based soft-macro assignment.

  45. HM SM Floorplanning and Soft-Macro Area Extraction HM HM

  46. Force-directed-based Placement HM SM4 HM SM2 SM3 HM SM1 HM

  47. Soft-macro Placement Y SM1 SM1 SM2 SM4 SM2 X SM4 SM3 SM3

  48. HDL Description Synopsys (Design Compiler) The Experimental procedure: Design Synthesis Structural-tree Construction SM Formation Netlist

  49. Netlist SM Placement Cadence (Silicon Ensemble) Cadence (Silicon Ensemble) Cadence (HLDS) Chip Layout The Experimental Procedure: Floorplanning and P&R

  50. Cadence (HyperExtract) Timing AVANT! (STAR-DC) Synopsys (Design Time) Chip Layout The Experimental Procedure: Timing Analysis

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