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Verilog-HDL

Verilog-HDL. Reference: Verilog HDL: a guide to digital design and synthesis, Palnitkar, Samir Some of slides in this lecture are supported by Prof. An-Yeu Wu, E.E., NTU. OUTLINE. Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling

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Verilog-HDL

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  1. Verilog-HDL Reference: Verilog HDL: a guide to digital design and synthesis, Palnitkar, Samir Some of slides in this lecture are supported by Prof. An-Yeu Wu, E.E., NTU.

  2. OUTLINE • Introduction • Basics of the Verilog Language • Gate-level modeling • Data-flow modeling • Behavioral modeling • Task and function

  3. Verilog HDL (continue) • Invented by Philip Moorby in 1983/ 1984 at Gateway Design Automation • Enables specification of a digital system at a range of levels of abstraction: switches, gates, RTL, and higher • Initially developed in conjunction with the Verilog simulator

  4. Verilog HDL • Verilog- based synthesis tool introduced by Synopsys in 1987 • Gateway Design Automation bought by Cadence in 1989 • Verilog placed in public domain to compete with VHDL – Open Verilog International (OVI) IEEE 1364 -1995 and • revised version IEEE 1364 -2001

  5. What is Verilog HDL ? • Mixed level modeling • Behavioral • Algorithmic ( like high level language) • Register transfer (Synthesizable) • Structural • Gate (AND, OR ……) • Switch (PMOS, NOMS, JFET ……) • Single language for design and simulation • Built-in primitives and logic functions • User-defined primitives • Built-in data types • High-level programming constructs

  6. Basic Conventions • Verilog is case sensitive – Keywords are in lowercase • Extra white space is ignored – But whitespace does separate tokens • Comments – One liners are // – Multiple lines /* */ – Comments may not be nested

  7. OUTLINE • Introduction • Basics of the Verilog Language • Overview of Verilog Module • Identifier & Keywords • Logic Values • Data Types • Numbers & Negative Numbers • Gate-level modeling • Data-flow modeling • Behavioral modeling • Task and function

  8. Overview of Verilog Module Test bench

  9. Basic unit --Module modulemodule_name (port_name); port declaration data type declaration module functionality or structure Endmodule

  10. D-FlipFlop module D_FF(q,d,clk,reset); output q; //port declaration input d,clk,reset; // data type declaration reg q; always @ (posedge reset or negedge clk) if (reset) q=1'b0; else q=d; endmodule

  11. Instance • A module provides a template which you can create actual objects. • When a module is invoked, Verilog creates a unique object from the template • The process of creating a object from module template is called instantiation • The object is called instance

  12. Instances module adder (in1,in2,cin,sum,cout); ....... endmodule module adder8(....) ; adder add1(a,b,1’b0,s1,c1) , add2(.in1(a2),.in2(b2),.cin(c1),.sum(s2) ,.cout(c2)) ; ..... endmodule Mapping port positions Mapping names

  13. T-FlipFlop module T_FF(q,clk,reset); output q; input clk,reset; wire d; D_FF dff0(q,d,clk,reset); // create an instance not n1(d,q); endmodule

  14. Identifier & Keywords • Identifier • User-provided names for Verilog objects in the descriptions • Legal characters are “a-z”, “A-Z”, “0-9”, “_”, and “$” • First character has to be a letter or an “_” • Example: Count, _R2D2, FIVE$ • Keywords • Predefined identifiers to define the language constructs • All keywords are defined in lower case • Cannot be used as identifiers • Example:initial, assign, module, always….

  15. Top level block Sub-block 1 Sub-block 1 Sub-block 1 Sub-block 1 Leaf cell Leaf cell Leaf cell Leaf cell Leaf cell Leaf cell Leaf cell Leaf cell Hierarchical Modeling Concepts

  16. Hierarchical Modeling Concepts • Module ripple_carry_counter(q,clk, reset); • Output [3:0] q; • Input clk, reset; • T_FF tff0(q[0], clk, reset); • T_FF tff1(q[1], q[0], reset); • T_FF tff0(q[2], q[1], reset); • T_FF tff0(q[3], q[2], reset); • endmpdule

  17. q 。 d q clk ○ Hierarchical Modeling Concepts • module T_FF(q, clk, reset); • output q; • input clk, reset; • wire d; • D_FF dff0(q, d, clk, reset); • not na(d, q); • endmodule

  18. Hierarchical Modeling Concepts • module D_FF(q, d, clk, reset); • output q; • input d, clk, reset; • reg q; • always @(posedge reset or negedge clk) • if (reset) • q=1’b0; • else • q=d; • endmodule

  19. Ripple carry counter T_FF (tff0) T_FF (tff1) T_FF (tff2) T_FF (tff3) D_ FF Inverter D_ FF Inverter D_ FF Inverter D_ FF Inverter 4-bits Ripple Carry Counter

  20. Exercise • module FullAdd4(a, b, carry_in, sum, carry_out); • input [3:0] a, b; • input carry_in; • output [3:0] sum; • output carry_out; • wire [3:0] sum; • wire carry_out; • FullAdd fa0(a[0], b[0], carry_in, sum[0], carry_out1); • FullAdd fa1(a[1], b[1], carry_out1, sum[1], carry_out2); • FullAdd fa2(a[2], b[2], carry_out2, sum[2], carry_out3); • FullAdd fa3(a[3], b[3], carry_out3, sum[3], carry_out); • endmodule

  21. Exercise • // FullAdd.V, 全加器 • module FullAdd(a, b, carryin, sum, carryout); • input a, b, carryin; • output sum, carryout; • wire sum, carryout; • assign {carryout, sum} = a + b + carryin; • endmodule

  22. Exercise • Implement a 16 bits full adder by using 4 bits full adders.

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